*AMD Demos First ClawHammer and SledgeHammer at IDF! Now Updated with Anand's Pics!*

[Bluga]

AMD has come a long way.

If you remember back then in the K7 days. Asus shipped their motherboards in plain white boxes with no advertisements or even support on their website, because they were afraid of repercussions from Intel. AMD had to beg VIA to come out with chipset other companies just sit there and watched.

Now, chipsets could very well be out (or sampling stage at least) in Q4 from no less than three chipset makers, and an additional two more will likely follow a quarter or two after. Additionally, AMD does not have to wait on chipset makers when they need to support a faster memory standard.

 

[Sohcan]

<< That's a good target. IA64 isn't selling well anyway. >>

Though this may be slightly boastful, here's what HP had to say about it:


<< If things go as planned, McKinley-based systems will quickly eclipse sales of the first Itanium. "I think we'll surpass [first-generation] Itanium sales in the first seven days," said Barry Crume, business manager for Itanium systems at HP >>

 

[NFS4]

<<

<< That's a good target. IA64 isn't selling well anyway. >>

Though this may be slightly boastful, here's what HP had to say about it:


<< If things go as planned, McKinley-based systems will quickly eclipse sales of the first Itanium. "I think we'll surpass [first-generation] Itanium sales in the first seven days," said Barry Crume, business manager for Itanium systems at HP >>

>>


Haha, that isn't saying much for Itanium

 

[PlatinumGold]

My opinion is that the Hammer will not be as good of a CPU as you might think. It uses unnesessary old technology (x86) and can't be compared to Intel's Itanium. It's very much like the 386, carrying all the unnesessary heritage of old, obsolete CPUs. That explains why we still have only 640K of 'main' memory which seems ridiculous. Hammer is a step back.

there is NO WAY the hammer is a step back. it might only be a half step forward, but to say that it is a step back is just plain stupid.

 

[RanDum72]

I second that, platinumgold.

 

[AGodspeed]

Geared, you should probably read AMD's Hammer White Paper.

 

[ElFenix]

dell probably outsells itanium (in terms of units shipped) every second or so.

 

[ST4RCUTTER]

My opinion is that the Hammer will not be as good of a CPU as you might think. It uses unnesessary old technology (x86) and can't be compared to Intel's Itanium. It's very much like the 386, carrying all the unnesessary heritage of old, obsolete CPUs. That explains why we still have only 640K of 'main' memory which seems ridiculous. Hammer is a step back.

Yeah, you're probably right.

6.4GB/s vs. 2.1GB/s bandwidth processor
800Mhz FSB vs. 266Mhz FSB
Better branch prediction
Additional pipeline stages
Integrated memory controller
64-bit extensions in addition to 32-bit
Integrated heatspreader
SOI
SSE2

Man, what the hell was AMD thinking. We keep going like this and we'll be in the Stone Age!!

 

[AGodspeed]

<< My opinion is that the Hammer will not be as good of a CPU as you might think. It uses unnesessary old technology (x86) and can't be compared to Intel's Itanium. It's very much like the 386, carrying all the unnesessary heritage of old, obsolete CPUs. That explains why we still have only 640K of 'main' memory which seems ridiculous. Hammer is a step back.

Yeah, you're probably right.

6.4GB/s vs. 2.1GB/s bandwidth processor
800Mhz FSB vs. 266Mhz FSB
Better branch prediction
Additional pipeline stages
Integrated memory controller
64-bit extensions in addition to 32-bit
Integrated heatspreader
SOI
SSE2

Man, what the hell was AMD thinking. We keep going like this and we'll be in the Stone Age!! >>

Not to mention AMD's 8000 Series of chipsets, HyperTransport, and, oh yeah, on-die support for dual cores (functions like HyperThreading) in the future.

 

[KevDODOUBLEG]

Here's an article on FiringSquad: AMD: It's Hammer Time!

 

[capodeloscapos]

I think AMD has an Ace, and it will be the prices, which are going to make Intel go down to the Earth. Trust me, I know exactly what I´m doing.
PD: In Argentina, Sledge used to say that, but I don´t know if the translation is correct.

 

[jhu]

i don't quite understand itanium. why would i get a $14k itanium system over a similarly priced ibm rs/6000?

 

[CocaCola5]

How much will it cost and will it be quantum leap ahead of a p4? I doubt it'ill be aggressively priced, looking at how AMD has significantly jacked up its processor asp.

 

[BD231]

if it's true then so much for Northwood's 533 FSB.

The Northwood dosent run a true 533mhz FSB, its a quad pumped 133mhz bus, which dosent mean jack to me. 133 is 133.

 

[AGodspeed]

<< How much will it cost and will it be quantum leap ahead of a p4? I doubt it'ill be aggressively priced, looking at how AMD has significantly jacked up its processor asp. >>

Well, consider that just today Fred Weber said that ClawHammer processors will be on SALE during the 4th quarter of this year. Lets just say for arguments sake that you can purchase ClawHammer 3400+ (that's its debut PR rating) sometime in December. By then, the best I've seen Intel will release is a 2.8GHz Pentium 4. If a ClawHammer 3400+ is indeed the performance equivalent of a 3.4GHz Pentium 4 (which it has to be obviously) then that would mean that ClawHammer right off the bat will have a 21.43% performance advantage over Intel (of course it will vary depending on the application, but that'll be the average). Quite a huge performance lead, especially when you consider its 64-bit functionality. For arguments sake, lets say ClawHammer 3400+ slips to the 1st quarter of next year. By then the best Intel will have is a 3GHz Pentium 4 (according to roadmaps). ClawHammer 3400+ would still have a considerable performance advantage, at 13.33%.

Will ClawHammer debut at a prohibitively high cost? Well, that's very difficult to predict. Assuming that AMD makes a half-way decent profit this year (they expect to make a profit starting from the 2nd quarter moving through the end of 2002) then that will likely lower ClawHammer's debut price. However, I think it's safe to assume that ClawHammer 3400+ will be around the same price as Intel's flagship at whatever date ClawHammer debuts, as has been AMD's tradition for a while now.

AMD is realizing some of their weaknesses by providing a heat spreader for ClawHammer and by supporting SSE2 instructions (I think ClawHammer will actually have larger support for SSE2 than the Pentium 4, not sure though).

Either way, ClawHammer looks great, especially in the distant future.

 

[Novgrod]

AGodSpeed, do you think Intel will sit on its haunches while the clawhammer decimates its p4? If a p4 can get up to 2.6 ghz today, couldn't they very reasonably improve to > 2.8 ghz by december? How flexible are these roadmaps anyway?

Don't get me wrong; I fully expect the clawhammer to reestablish AMD's performance title, but 21% is a whole lot of %.

 

[sparks]

You never know exactly what Intel has up their sleeves. They may push Hyperthreading down to the consumer levels and claim that that their 2.8GHz P4 with Hyperthreading is the equivelent of a 3.64GHz P4 without HT (given the claims of 30% or greater performance increase from HT). Regardless, I think the consumer will benefit greatly!!!

 

[Sohcan]

<< The Northwood dosent run a true 533mhz FSB, its a quad pumped 133mhz bus, which dosent mean jack to me. 133 is 133. >>

Then it sure is amazing that the P4 w/133MHz bus call pull STREAM benches in excess of 3.3GB/sec when, by your standards, it should only be capable of 1GB/sec. Look at bandwidth, not clockrate....with pipelined transactions, out-of-order queuing, and extensive data buffering, DDR and QDR buses are quite capable of achieving 80-90% of their theoretical bandwidth rates. Keep in mind that as a serial bus, Hammer's 16-bit 800MHz DDR HT implementation takes two bus cycles to complete a 64-bit DRAM word transfer (probably more, since HT is a packet-based protocol...I believe the command packet is another 64-bits).

 

[ST4RCUTTER]

Keep in mind that as a serial bus, Hammer's 16-bit 800MHz DDR HT implementation takes two bus cycles to complete a 64-bit DRAM word access.

Isn't RAMBUS currently using 16-bit words? Using that as an example, could we extrapolate an approximate performance number given a 400Mhz (800Mhz DDR) HT bus?

If I recall correctly, RAMBUS won't be using a 64-bit word address until late 2005 with the 32-bit version arriving beforehand. I believe the same article said that RDRAM would be running 300Mhz (1200Mhz quad-pumped).



edit: There's an incorrect point in my post above:

HT runs at 800Mhz (1600Mhz effectively). This means that the HT bus takes twice as many cycles to complete a 64-bit word, but runs 4 times faster than existing RDRAM @ 400Mhz (effective). It is also full-duplex, meaning that it can send and receive data at the same time. I don't know if RDRAM can be described in a similar fashion.


I found this cool link on HT while researching. HT seems as much an improvement as the chip itself!!

 

[BlvdKing]

I have nothing important to add to this thread except for this: I can't believe the hammer is this close. I remember hearing that AMD was working on the K8 shortly after the K7 was released. Now it looks like there is a good chance for it this year! The K7 had an amazing run though, albiet a bit short (3 - 4 years) considering how long Intel kept the P6 alive.

 

[AGodspeed]

<< AGodSpeed, do you think Intel will sit on its haunches while the clawhammer decimates its p4? If a p4 can get up to 2.6 ghz today, couldn't they very reasonably improve to > 2.8 ghz by december? How flexible are these roadmaps anyway?

Don't get me wrong; I fully expect the clawhammer to reestablish AMD's performance title, but 21% is a whole lot of %. >>

Understand that AMD and Intel are quite different positions.

Intel can't simply release a 2.6GHz tomorrow just because they're overclocking that well. Just because it overclocks to 2.6GHz doesn't mean you can get acceptable yields at that speed. And lets just say for arguments sake that Intel has been getting great 2.6GHz yields for a while now. That still wouldn't mean that Intel could release a 2.6GHz processor soon (btw, Intel is scheduled to release a 2.66GHz P4 in September, at the very earliest). Intel would make considerably more profit by milking their current flagship 2.2GHz P4 for as long as possible than to release a 2.6GHz P4 and drastically kill their ASPs (average selling prices).

AMD on the other hand is actually forced to move to the K8 Hammer architecture, the K7 core is reaching its physical limits. The Athlon won't have much juice left once they release their 2.2GHz Athlon XP "Barton" core processor in Q4 this year, making a K8 ClawHammer release in Q4/Q1 sensible, all while not killing AMD's ASPs. The fact that the performance of ClawHammer could be "earth shattering" will just be a big bonus for AMD when ClawHammer debuts. Remember, Intel and AMD are far more interested in profit (and market share too) than outperforming the competitor.

 

[jpprod]

Keep in mind that as a serial bus, Hammer's 16-bit 800MHz DDR HT implementation takes two bus cycles to complete a 64-bit DRAM word transfer (probably more, since HT is a packet-based protocol...I believe the command packet is another 64-bits).

You should note that while on current system architectures everything the CPU needs is transferred via the FSB, on Hammer processors the HT links are only used for I/O, not memory access (excluding MP systems in which interprocessor data exchange is necessary). Hammer has an integrated memory controller, and thus a completely separate set of traces that connect the processor directly into DDR memory.

 

[Sohcan]

<< Isn't RAMBUS currently using 16-bit words? Using that as an example, could we extrapolate an approximate performance number given a 400Mhz (800Mhz DDR) HT bus? >>

Now we're getting our terminologies mixed up. The HT links in Hammer have a clock rate of 800MHz, with a transfer rate of 1600 MTransers/sec. It's a 16-bit bi-directional bus with 3.2GB/sec in each direction, for 6.4GB/sec total per link.



<< You should note that while on current system architectures everything the CPU needs is transferred via the FSB, on Hammer processors the HT links are only used for I/O, not memory access (excluding MP systems in which interprocessor data exchange is necessary). Hammer has an integrated memory controller, and thus a completely separate set of traces that connect the processor directly into DDR memory >>

Completely right, consider it a 64-bit IO packet rather than memory data. (though in addition, HT would be used for memory data for DMA)

 

[ST4RCUTTER]

Now we're getting our terminologies mixed up. The HT links in Hammer have a clock rate of 800MHz, with a transfer rate of 1600 MTransers/sec. It's a 16-bit bi-directional bus with 3.2GB/sec in each direction, for 6.4GB/sec total per link.

I understand now...and the HT .pdf describes that as well, albeit at a level I can just barely grasp. So basically we're looking at a 3.2GB/s path each way for I/O and standard DDR FSB speeds for memory access (333Mhz DDR currently).

 

[AGodspeed]

...for 6.4GB/sec total per link.

Ah yes, me likes bandwidth.