I though earlier estimates had it at 175mm², but I guess that 180mm² is "rund 180 mm² große Chip".
Anyway, plugging the SqrtRt of 180 (13.4mm) into this:
caly-technologies.com
wafer yield calculator with a defect rate of 0.09 per cm² gives us this (TSMC gave that defect rate a good while back so it should hopefully be a lot better now):
Your 320 figure was assuming no defects.
The calculator expects 269 good dies per wafer although not all the 47 'defect' dies would be waste as with some of them they could disable a CU or core, etc.
On the other hand, not all good dies will bin at the kind of clocks or voltages they want, but since Cezanne isn't a single SKU console those should be useable somewhere.
$8000 is a bit optimistic, 7nm wafer are meant to be more like $12000+.
Anyway while wafers are scares, I guess the comparison for AMD is how many CCDS could they make instead?