With the release of Alder Lake less than a week away and the "Lakes" thread having turned into a nightmare to navigate I thought it might be a good time to start a discussion thread solely for Alder Lake.
When Skylake launched with DDR4, they still had a limited number of boards that supported DDR3:I'm convinced that DDR4 is the way to go if you were going to buy at launch. This always happens with new memory but unlike last time Intel changed memory you have a choice.
When Skylake launched with DDR4, they still had a limited number of boards that supported DDR3:
It appears to be a similar situation this time with DDR5.
Sort of. If you are a marketeer.
Looks like all the K chips will be based on the 8+8 die. So will the 6 core die be used only for locked, low frequency chips? Will they also bin these chips or will they waste the golden samples? Why?
Something interesting that came out of the reddit AMA is that in testing Intel found that some games do like the DDR5 bandwidth and others as we know prefer DDR4 due to lower latency.
In their 11900K vs 12900K slide there were some really big gains for some games but looking at them a lot have more going on CPU wise. It seems that it may be possible that some of these gains can be attributed to DDR5 bandwidth (anybody with a fast ram in a comet or rocket lake system want to compare improvements in the likes of Troy, hitman 3 etc at 3200 C14 vs 4400 C36 to get an idea how much bandwidth impacts some of those games that saw huge gains?).
At the other end of the scale there are a fair number of games with minimal improvements (and 1 regression). I think it is quite possible that in a DDR4 system the games on the left hand side end up with a better showing than Intel showed but some of the games with the big 20+% gains do worse.
It will be very interesting to find out.
What, a 563 page thread about 6 different generations of product, all being argued about concurrently, isn't easy to follow?
Well, newegg has quite a few DDR5, none are ECC
DDR5 has halfway implemented ECC: all DDR5 has ECC for everything that occurs on the memory module. So if a memory chip has a bit flip, it will be caught and corrected. But DDR5 does not have automatic full-system ECC. Meaning if a bit flip occurs during data transmission, that it will not be caught without extra resources.ECC is built into the module itself.
Do you have a source for that? It seems reasonable that they only are running the 8+8 die right now and will be using the best 6-core chips for high-end mobile. But, they theoretically could have used the 6+8 die for the 12600K and 12600KF. So, is there evidence that they are not doing so?Looks like all the K chips will be based on the 8+8 die. So will the 6 core die be used only for locked, low frequency chips? Will they also bin these chips or will they waste the golden samples? Why?