So with 64 data lines that means the cpu can read/write to memory 8 bytes at a time?
this is where it may get kinda confusing.. typically when the data bus width is rated it's rated by the number of bits it can read
or write. since amd's single channel 64-bit processors can read
and/or write at the same time.. it's considered to have a 128-bit data bus, which would yield 16 bytes.. however, since it can't read or write twice at the same instant it's not exactly true to being 128-bits wide.
..For instance, on the P4, the data bus is 64-bits wide. On Opteron, it's 128-bits wide.
p4 with dual-channel has a 128-bit wide bus.
Because the P4 can operate internally so much faster than the Mobo can, there is a bottle neck at the chip's pins: using more pins helps alleviate this, but doesn't affect the internal operations significantly.
mm.. you don't know what you're talking about. the p4 isn't the only processor out there with that bottleneck and to make such a statement proves your ignorance. any and every processor that has the cpu running at a different speed than the memory has a bottleneck at that point. the fact that the p4 is 32-bits only means that the general purpose registers are 32-bits wide.. so up until data reaches those registers, it won't be any different than if the p4 was a 64-bit processor.
The AMD64 chips actually address 48-bit (I think) memory spaces, not a full 64 bits (which would be a tad bit of overkill on today's, or even tomorrow's, systems)
yea, amd64 has a 48-bit address bus.. so do some of the p4's. only problem is.. you can't turn "on" the extra 16-bits without an operating system that supports pae (physical address extensions)- pretty much windows server os' only.
on another note.. a system that fully utilizes 64-bits would be awesome! 2 exabytes of ram.. imagine being able to say that today. most people would be like 'wtf is that?'
one last thing.. how old are you people?! i took a class on this last semester.. and we worked with p4 architecture. i've never even heard of the hc6811...