This will probably end up being like asynchronous logic - something that seems like it would be a potential huge win but isn't used outside a few tiny niches. For asynchronous logic, due to a lack of tools because no one would be willing to risk the sort of impossible to reproduce bugs that would result, for "adaptable transistors" because almost no one is using germanium as a base layer anymore - even BJTs have largely moved to silicon or gallium arsenide.
The other problem is that transistors are basically free. Even if this worked for standard silicon, Apple has an SoC with 57 billion transistors, and the N3 version will likely hit nearly 100 billion. It isn't like you could reduce that number by 85%, since this doesn't work for cache or cache like structures which is where so many transistors are consumed. You could probably realize some savings (without full blown tool support) in regular repeating structures like inside a GPU core or DSP blocks.
Even there the benefit remains unclear - just because you reduce the number of transistors by 85% in certain areas doesn't necessarily mean you reduce the AREA by 85% - because these transistors need additional control to reconfigure them, and maybe have other differences in how they are made. If you really could shrink the area used by those types of structures by 85% you might save maybe 25% of the overall area of a typical modern SoC. Nice, but hardly a game changer. There's also no reason to believe (despite what the article says) that this would result in any power savings beyond per transistor leakage current. So sounds nice, but would hardly make a major impact on the end user that asynchronous logic would if it were ever made to work.