A memory divider doesnt hurt any performance right?

[DfiDude]

Im just wondering if a mermory divider would hurt performance or should people go with a 1:1 ratio?

 

[Jiggz]

A 1:1 ratios is the preferred method. Using a Memory Divider works also though there will a small lag in performance.

 

[DfiDude]

But doesnt 1:1 ratio put more pressure on cpu or something like that?

 

[Peter]

No. Besides, all that divider/asynchronous panic applies only to classic north-bridge-centric architectures. With AMD64 CPU-integrated RAM controllers, there is no FSB, hence nowhere to run the RAM in sync with. Here, RAM always operates on a divider down from CPU _core_ clock, e.g. CPU/13 when you run DDR400 on a 2.6 GHz CPU. You're not on a bus:bus ratio, you're on a core:bus divider. Always.

Yes this concept is often misrepresented by people who cannot or will not grasp the new concept. This apparently includes Anandtech authors and BIOS user interface designers. *rolls eyes*

 

[bob4432]

Originally posted by: Peter
No. Besides, all that divider/asynchronous panic applies only to classic north-bridge-centric architectures. With AMD64 CPU-integrated RAM controllers, there is no FSB, hence nowhere to run the RAM in sync with. Here, RAM always operates on a divider down from CPU _core_ clock, e.g. CPU/13 when you run DDR400 on a 2.6 GHz CPU. You're not on a bus:bus ratio, you're on a core:bus divider. Always.

Yes this concept is often misrepresented by people who cannot or will not grasp the new concept. This apparently includes Anandtech authors and BIOS user interface designers. *rolls eyes*

you are assuming he is using a new cpu, but what about a skt478 P4 that supposedly needs the bandwidth?

say he is running his a64 venice @ 2.7GHz and the memory at ~200MHz to get to the desired fsb. won't this affect performance?

 

[SrGuapo]

Originally posted by: bob4432

Originally posted by: Peter
No. Besides, all that divider/asynchronous panic applies only to classic north-bridge-centric architectures. With AMD64 CPU-integrated RAM controllers, there is no FSB, hence nowhere to run the RAM in sync with. Here, RAM always operates on a divider down from CPU _core_ clock, e.g. CPU/13 when you run DDR400 on a 2.6 GHz CPU. You're not on a bus:bus ratio, you're on a core:bus divider. Always.

Yes this concept is often misrepresented by people who cannot or will not grasp the new concept. This apparently includes Anandtech authors and BIOS user interface designers. *rolls eyes*

you are assuming he is using a new cpu, but what about a skt478 P4 that supposedly needs the bandwidth?

say he is running his a64 venice @ 2.7GHz and the memory at ~200MHz to get to the desired fsb. won't this affect performance?

Yes, but if his RAM cannot handle 270 MHz, then he must use a divider. Basically, when you OC, you want to find the highest CPU clock, and the highest mem clock (at whatevcer timings. Then set a divider that will give you the fastest RAM speed while still under the max speed you found earlier.

If desired, you can lower the multi to get a different RAM divider that may let you speed up the RAM a bit...

Edit: Yes it does depend on the CPU. I was assuming A64. Any other procs (al Intel procs and older AMD procs) will have a memory controller off the chip, meaning the RAM divider will hurt performance a bit...

 

[bob4432]

Originally posted by: SrGuapo

Originally posted by: bob4432

Originally posted by: Peter
No. Besides, all that divider/asynchronous panic applies only to classic north-bridge-centric architectures. With AMD64 CPU-integrated RAM controllers, there is no FSB, hence nowhere to run the RAM in sync with. Here, RAM always operates on a divider down from CPU _core_ clock, e.g. CPU/13 when you run DDR400 on a 2.6 GHz CPU. You're not on a bus:bus ratio, you're on a core:bus divider. Always.

Yes this concept is often misrepresented by people who cannot or will not grasp the new concept. This apparently includes Anandtech authors and BIOS user interface designers. *rolls eyes*

you are assuming he is using a new cpu, but what about a skt478 P4 that supposedly needs the bandwidth?

say he is running his a64 venice @ 2.7GHz and the memory at ~200MHz to get to the desired fsb. won't this affect performance?

Yes, but if his RAM cannot handle 270 MHz, then he must use a divider. Basically, when you OC, you want to find the highest CPU clock, and the highest mem clock (at whatevcer timings. Then set a divider that will give you the fastest RAM speed while still under the max speed you found earlier.

If desired, you can lower the multi to get a different RAM divider that may let you speed up the RAM a bit...

Edit: Yes it does depend on the CPU. I was assuming A64. Any other procs (al Intel procs and older AMD procs) will have a memory controller off the chip, meaning the RAM divider will hurt performance a bit...

any benches on "a bit" on say a P4 with a 3:2 and 5:4 divider since it was the memory bandwidth starved cpu?

 

[furballi]

Going from DDR400 to DDR333 will cost you about 50MHz CPU core speed. A drop to DDR266 another 50MHz.... It's best too stay at or above DDR333.

Course if you can gain more than 50MHz with the use of a lower memory divider (usually +5MHz FSB), then you will come out ahead!