A long rant about how I hate Socket AM4 but love the Zen SoCs, and how I would like Ryzen/EPYC Embedded alternatives

[B-Riz]

The cost would have been substantial. There is still a significant (>$10 per port) patent license cost associated with 10GbE. Presumably, they have a licensing contract that allows them to not pay it for parts that have it disabled.

The "home networking revolution" will come in 2023 (IIRC), which is when the relevant patents expire and 10GbE becomes cheap.

Right, I was thinking that when I can walk into Best Buy and buy a 10GbE router+switch for what gigabit costs now, it is officially here.

 

[VirtualLarry]

Right, I was thinking that when I can walk into Best Buy and buy a 10GbE router+switch for what gigabit costs now, it is officially here.

But 1GbE NICs are essentially "free" with the ATX motherboards from the last 10 years (not really free, but included built-in as standard). Once mobo companies switch, and start building in faster onboard NICs, that will propel the market for things like switches, and that will drive down the costs for everyone, due to innovation and economies of scale. (Google "Turn the Flywheel" book, for more info on that.)

TP-Link and a few others, have introduced, not just 10GbE with multi-gig port switches, but also some 2.5GbE 8-port switches with 2x 10GbE SFP+ ports for uplink. RealTek also introduced not too long ago, a family of lower-cost 2.5GbE NIC chips, both USB3.1 and PCI-E, so that appears to be coalescing as the new "minimum standard". As well, because of Wave2 AC access points needing more than 1GbE to handle AC1750/AC1900/AC2100 traffic over the wifi.

 

[Tuna-Fish]

But 1GbE NICs are essentially "free" with the ATX motherboards from the last 10 years (not really free, but included built-in as standard). Once mobo companies switch, and start building in faster onboard NICs, that will propel the market for things like switches, and that will drive down the costs for everyone, due to innovation and economies of scale. (Google "Turn the Flywheel" book, for more info on that.)

But right now the cost floor is not based on how much it costs to make the things, it's based on "we have to pay a lot of money to license the patents". 1GbE NICs got practically free because their relevant patents expired, and then people were free to innovate on how to make the systems as cheaply as possible. Right now, it doesn't really matter if you figure out how to build a 10GbE switch for $50, because you have to pay the license cost on top of that, and for a switch with a lot of ports, that will be hundreds of dollars. Just because it's an open standard doesn't mean it's free to use, the patents are just licensed under FRAND terms.

 

[abufrejoval]

I concur with most of what you say: I also feel that the AM4 socket is doing more damage than good for the AMD ecosystem.

First of all, pre-Ryzen AM4 was entry level, cheap stuff: Average motherboard prices below $100, not a significant factor when you had to bleed hundreds for a sizeable chunk of RAM, had to upgrade to DDR4 etc. just to get to the point were you could then buy a Ryzen.

So to establish a new socket with Ryzen and *then* to stick with it, might have been a better choice than being tied to a legacy enthusiasts never cared about and mortal users would never upgrade anyway.

Well I know they actually did that. It's called ThreadRipper, but...

As you say, Ryzen is really an SoC. So there is practically no value in the motherboard itself. It's little more than a glorified multi-I/O card with wires for slots and DIMM sockets and those ports that don't belong there.

One way to solve the chipset/motherboard value dilemma would be to just move it back into such an I/O card, like in the old days, make the motherboard truly passive, more of a back-plane. I know single slot doesn't give enough port space out back, don't take it too literally!

But let's look at the source of our pain for a moment: We are upset at the shortcomings of AM4 only, because Zen doesn't have them: Only AM4 imposes them. We should really relish just how genius the Zen architecture base was designed. And if you had enough volume, you could do lots of things with it and start by getting rid of that stupid socket and using BGA variants.

Yet as bad as AM4 is, I can't help but agree with AMD's reasoning at the time, that competing or rather thrashing Intel on price was top priority. So matching exactly what Intel could offer with their hard-wired CPU/chipset architecture in terms of functionality was more important than offering extra functionality that far too few would appreciate and pay for to make it cost efficient, like 10G.

But as the industry adopts more Zen, the inherent flexibility at the base of the design that you and I appreciate both, will hopefully play out in attractive future products at good economy, because AMD has done its home-work with Infinity Fabric.

Just gotta be patient and keep on bying kit from AMD to make sure they get there...

 

[Shivansps]

I dont think that AM4 is the problem, im convinced that AMD enforces the use of a chipset on products with form factor mitx or larger.

 

[abufrejoval]

I dont think that AM4 is the problem, im convinced that AMD enforces the use of a chipset on products with form factor mitx or larger.

Unfortunately that's the level of contractual detail that the public just doesn't get to see...

But I am not arguing for leaving out the actual chips in the chipset: You are going to need those very likely in any system. Perhaps they should go to a different place than the motherboard and perhaps you should actually have two or even three (different ones?) of them, now that with the Ryzen 3000 and PCIe 4.0 you may want to sub-divide the lanes with much more flexibility. To me PCIe 4.0 cries for flexible switches rather than fixed lanes on slots.

And I doubt that the ASmedia/AMD chipsets would know if the incoming PCIe (or IF?) lanes come from an AM4 socket or from BGA traces, so there isn't even an issue with AMD wanting to make extra money from those "southswitches".

Your comment makes a lot of sense together with the other comment in this thread, that argued that patent licenses were an issue. It would mean that AMD and IP vendors tie those licenses to the southswitch (because it's not really a bridge...), not the SoC containing the CPU.

The Zen architecture and the Infinity Fabric offer so much freedom and flexibility that one cannot help but think that there are better solutions to use cases we have run into.

And with just two DRAM channels on now a maximum of 12 and soon perhaps 16 cores, I can't help but think that returns will diminish severely, when AMD themselves tout how much of an advantage eight channels on Epic represent over 'just' six channels on Xeon SP. Their relative silence on the four channels for ThreadRipper speak loudly to engineers.

Thanks for your info, AM4 itself may just represent deeper issues, I see a lot of common ground here.

 

[Shivansps]

Well they can actually run dual channel DDR5 on AM4 providing enoght bandwidth for those 16C or a 8C+IGP... There is a chance for AM5 to be just a re-arranged AM4 pinout for power delivery. As PCI-E 4.0 also fixed Picasso issue with main PCI-E bandwidth. So even if next gen APU are 8x on main PCI-E that would not matter.

To me the mayor problem lies on exactly on the things we dont know about, Asrock only being able to make a "A300" motherboard on STX is a big red flag. IN FACT, it says exactly this on the AMD website...

AMD X300 and A300 Chipsets
Ideal for the smallest form factors
To satisfy customers who value the smallest form factors, AMD’s X300 and A300 chipsets provide processor-direct access for excellent performance. The enthusiast-oriented X300 chipset is perfect for enthusiasts and overclockers, while the A300 chipset is geared toward practical users who need simple, small solution.2,3

It cant be more clear, A300 is only allowed on small form factors, smaller than ITX, and A300 itseft it is the SoC...

 

[moinmoin]

When talking about Ryzen as SoC one needs to keep in mind that desktop Ryzen is more defined through AM4 than it is through the capability of the (server grade) Zeppelin (so Zen and Zen+) die. We don't know what capabilities the Zen 2 IOC for Ryzen will have. Considering with Zen 2 the IOC is no longer shared with the Epyc chips it may well be the case that capabilities that are never used on AM4 anyway (like the 8 superfluous PCIe lanes) will all be cut from the Zen 2 Ryzen IOC.

 

[Insert_Nickname]

(like the 8 superfluous PCIe lanes)

Those are not superfluous. They're reconfigured as SATA (2x SATA or a PCIe 3.0 x2 NVME port) and 4 USB3 ports. Somewhat like Intel's FlexIO.

 

[moinmoin]

Those are not superfluous. They're reconfigured as SATA (2x SATA or a PCIe 3.0 x2 NVME port) and 4 USB3 ports. Somewhat like Intel's FlexIO.

My point was that the AM4 platform, unlike the server SoC implementation on the Zeppelin die, is not flexible so the Ryzen IOC may no longer have the flexibility people in this thread lament about AM4 not using.

 

[deathBOB]

Seems like something that is more relevant to the laptop space. Are on chip io features used more there?

 

[moinmoin]

Seems like something that is more relevant to the laptop space. Are on chip io features used more there?

Yes and no. Laptop and mobile chips are ideally and commonly integrated SoCs since that keeps power usage low compared to having separate chip for different features. But the IO capability of Zeppelin we are talking about in this thread are way too expansive for mobile usage, as a result the power usage of the uncore is too high for that space. That's why Raven Ridge is more limited in its IO capability.

 

[zir_blazer]

I think that what amd6502 was suggesting was actually the opposite- that AMD is avoiding paying the companies who supplies the IP integrated into their SoC. Which is entirely feasible! AMD didn't go out and develop an in-house 10GbE controller. They licensed the design from an external company to put onto their die. Presumably AMD has to pay a per-chip licensing fee for this IP, but if the silicon is fused off and unusable then perhaps they don't need to pay the license. Meaning that AMD can reduce their costs, and either pass the savings onto consumer customers or just improve their own profit margins.

You should also bear in mind that OEMs love sockets. A socket means that they can take a single motherboard design and easily offer a range of models just by slotting in a different CPU and different capacity DIMMs. They only need to stock and maintain a single motherboard model, and it significantly simplifies things for them.

So basically, what you're trying to say is that AM4 and SP3 doesn't offer the 10G MACs since AMD would have to pay licensing for each Processor unit sold, regardless if the feature gets used or not? Still, this makes the position of Ryzen and EPYC Embedded rather stupid, since with a single exception, they all offer the 10G MACs, yet if you look at actual products using the SoCs, it is extremely rare that someone ships them paired with the 10G PHYs. If such was the case, AMD is paying licensing for a feature that almost no one is using in two entire lines. It would have been more sensible to make SKUs with the 10G MACs enabled and others with them disabled, instead of having all embedded consumers subsidizing an underused feature.
...but all this is speculation since we don't know the in depth details.

As far that I know about OEMs, they like lower costs, and mostly nonupgradeable consumers systems. A soldered Processor seems to fit those definitions perfectly. They still can use the same base Motherboard, the soldered Processor isn't too different to when there is a base Motherboard model that includes extra possible manufacturing options (Like when you see a Motherboard that has some solder pads for a controller and connectors, and a more expensive version that has them populated. Examples: Supermicro X11SSH-TF and X11SSH-CTF, the latter includes a SAS Controller that in the former is unpopulated). As such, I don't think that going embedded could hurt their logistic chain at all.

I concur with most of what you say: I also feel that the AM4 socket is doing more damage than good for the AMD ecosystem.

Actually, AM4 can be considered great for people that upgrade often, and historically, AMD had Sockets with more overall longetivity than Intel (Even when Intel had Socket continuity, like LGA 775, they still forced you to purchase a new Chipset, thus Motherboard). That a launch day Ryzen Motherboard can potentially support a Processor with twice the cores and two generations worth of architectural improvements is not something to belittle. Is just that in the world of SoCs such continuity means that they have to follow the Socket rules, yet AM4 doesn't even maximize the original Zeppelin. I think that the blame should be placed on the fact that AM4 was released early for Bristol Ridge APUs for OEM systems.

Well I know they actually did that. It's called ThreadRipper, but...

Actually, TR Socket TR4 is physically the same than EPYC SP3, AMD just reused it. TR is far bigger than it should be. The dual die EPYC Embedded actually proves that.

But let's look at the source of our pain for a moment: We are upset at the shortcomings of AM4 only, because Zen doesn't have them: Only AM4 imposes them. We should really relish just how genius the Zen architecture base was designed. And if you had enough volume, you could do lots of things with it and start by getting rid of that stupid socket and using BGA variants.

This is what I believe, too. For people that never gets to upgrade a core component of the platform during its useful lifetime, or for high volume low end where every penny may count, embedded makes a lot of sense. However, if you gave me the choice between a Socketed platform, and a soldered platform that were otherwise identical, chances are that I would have picked the socketed one if price was't much higher due to the upgrade possibilities, but here you have an embedded platform that has far more interesing features.

I dont think that AM4 is the problem, im convinced that AMD enforces the use of a chipset on products with form factor mitx or larger.

There is no material proof of that. We don't even know why the A300 was MIA during two years.

Also, there is no reason technical why a Ryzen Embedded can't take over the mITX segment. That is precisely what I want to see. A Raven Ridge based Ryzen Embedded V1000 has more I/O than a Socket AM4 equivalent, simply because the A300 adds nothing and AM4 cuts some of the SoC I/O. Anything related to licensing issues due form factor size is pure conjecture, the 10G MAC theory has better basis.

BTW, I just reminded that AMD said that while Ryzen was a SoC, that they still needed a Chipset because it was a "security processor" of some sort to validate a legit part combination or something along those lines. I'm too lazy at this moment to look around from which two years old article I got that info from.

When talking about Ryzen as SoC one needs to keep in mind that desktop Ryzen is more defined through AM4 than it is through the capability of the (server grade) Zeppelin (so Zen and Zen+) die. We don't know what capabilities the Zen 2 IOC for Ryzen will have. Considering with Zen 2 the IOC is no longer shared with the Epyc chips it may well be the case that capabilities that are never used on AM4 anyway (like the 8 superfluous PCIe lanes) will all be cut from the Zen 2 Ryzen IOC.

The I/O dies should have at the bare minimum to provide the same I/O than what the Sockets (Both AM4, TR4 and SP3) exposes. The AM4 version could technically have less I/O than what Zeppelin has since it has to match the Socket, not more. However, if they reuse them across multiple lines, like the same AM4 I/O die for the successor of the current embedded lines, it should have more features than exposed in AM4, and perhaps even more than the current embedded products (Seriously, they need 8 USBs).
In my opinion, TR will perhaps use the same I/O die than EPYC since it seems simpler than having to maintain three versions. I even have a theory about Socket unification or cross compatibility between the TR4 and SP3 lines, but that doesn't belong to this Thread.

Those are not superfluous. They're reconfigured as SATA (2x SATA or a PCIe 3.0 x2 NVME port) and 4 USB3 ports. Somewhat like Intel's FlexIO.

You didn't read the Thread at all, didn't you? The USB aren't part of a Flex IO type scheme, at least on Zeppelin. The "2x SATA or a PCIe x2 NVMe Port" are already included in the 24 lane count (16 for main Slot + 4 for these + 4 for Chipset). You're missing 8.

That's why Raven Ridge is more limited in its IO capability.

Actually, RR has more USBs than Zeppelin, 6 vs 4. These aren't exposed in AM4.

 

[Insert_Nickname]

You didn't read the Thread at all, didn't you? The USB aren't part of a Flex IO type scheme, at least on Zeppelin. The "2x SATA or a PCIe x2 NVMe Port" are already included in the 24 lane count (16 for main Slot + 4 for these + 4 for Chipset). You're missing 8.

I hate to say it, but you're plain wrong here. The Zeppelin die has 32 lanes, comprised of two 16 lane root complexes.

First ("graphics") complex can be split as x8/x8. There are even a few boards allowing an x8/x4/x4 arrangement. F.x. the ASUS B450-E.

The second ("FCH") complex is where it gets interesting. All 16 lanes are there and enabled. The first x4 is the "NVMe port" on most boards. the second x4 is used for the FCH, aka. the southbridge. The next four lanes comprise the SoC on-chip SATA controller, which also happens to support SATA Express, and so can function as a PCIe 3.0 x2 port. The last four lanes are used for 4 on-chip USB3 ports, for a total of 16 lanes.

 

[itsmydamnation]

usb have there own physicals, almost everything else is on the Designware G12 SERDERS


i had to go searching to find this old guy again:

 

[zir_blazer]

I hate to say it, but you're plain wrong here. The Zeppelin die has 32 lanes, comprised of two 16 lane root complexes.

First ("graphics") complex can be split as x8/x8. There are even a few boards allowing an x8/x4/x4 arrangement. F.x. the ASUS B450-E.

The second ("FCH") complex is where it gets interesting. All 16 lanes are there and enabled. The first x4 is the "NVMe port" on most boards. the second x4 is used for the FCH, aka. the southbridge. The next four lanes comprise the SoC on-chip SATA controller, which also happens to support SATA Express, and so can function as a PCIe 3.0 x2 port. The last four lanes are used for 4 on-chip USB3 ports, for a total of 16 lanes.

Seriously, read my first post. You got totally wrong what is on the second muxed controller. The 4 USBs are independent of the 32 lanes, they aren't muxed with anything. If you count them, you're at actually 36 things. Check this graph.
You can even go count lanes on an EPYC Embedded platform like the Supermicro M11SDV-8C+-LN4F, which on its Block Diagram at Page 18 shows you the standard 16x controller, 4 lanes for an Intel i350 NIC, 4 lanes for a M.2 Slot, 4 SATA, 1 lane for the ASPEED BMC, and 4 USBs (Check the names of the ones coming from the Processor, ignore the USB Hubs). That's a total of 33, which doesn't add up according to your counting method (That model is actually not exposing 3 PCIe lanes of the muxed controller).

 

[Shivansps]

There is no material proof of that. We don't even know why the A300 was MIA during two years.

Also, there is no reason technical why a Ryzen Embedded can't take over the mITX segment. That is precisely what I want to see. A Raven Ridge based Ryzen Embedded V1000 has more I/O than a Socket AM4 equivalent, simply because the A300 adds nothing and AM4 cuts some of the SoC I/O. Anything related to licensing issues due form factor size is pure conjecture, the 10G MAC theory has better basis.

BTW, I just reminded that AMD said that while Ryzen was a SoC, that they still needed a Chipset because it was a "security processor" of some sort to validate a legit part combination or something along those lines. I'm too lazy at this moment to look around from which two years old article I got that info from.

More proof that AMD own website saying that A300 is intended for the "smallest" form factors and by pure conincidence the only implementation of A300 was on SFF?

I know that AMD said that A300 needs a chipset. Ive been looking at the Asrock A300 itseft and the closer thing to a controller in there is a Nuvoton chip.

 

[zir_blazer]

Reviving this due to the inminent release of Zen 2...


As we know, whereas the Zeppelin die was a full blown SoC, AM4 Zen 2 (Matisse) has instead one or two CPU chiplets and an IO chiplet. However, from the perspective of the Processor as a whole unit, it is still a SoC. Moreover, for backwards compatibility, AMD had to make sure than whatever was exposed by Zeppelin is also exposed by the IO chiplet in a pin compatible format, so that the PCIe Lanes, SATA and USB Ports keep working if you drop Ryzen 3000 in existing AM4 Motherboards.
According to some info, Matisse IO chiplet and the X570 Chipset (And perhaps other derivatives) are based on the exact same design but manufactured in different nodes, the Matisse IO die is 12nm whereas X570 is 14nm. The Rome IO chiplet is an entirely different design and chances are that it is going to be used for ThreadRipper in a castrated format, unless AMD pulls out a third IO chiplet design, which I doubt given how similar ThreadRipper and EPYC 7000 are, and low ThreadRipper volume.

One of the problems with theorycrafting is that we don't know the full capabilities of the Matisse IO chiplet. For one, it seems that it has two widely different configurations, one in the AM4 package, which is limited in the exact same way that Zeppelin was due to Socket AM4 (24 PCIe Lanes, 4 USB), whereas in Chipset variant, there are things like the 128/144 Bits (Or 2 x 64/72?) Memory Controller and the Infinity Fabric links to connect to the CPU chiplets that are not exposed (Unless they're multiplexed into something else). The miscellaneous I/O seems to not be exposed, either, given the fact that it is already available on the AM4 Socket. The status regarding the 10G MACs is unknow, but given than it wasn't very popular in Ryzen Embedded and EPYC Embedded, it may be possible that it was removed, but we have to wait for a product to use them to know if they are still there.

What info we have available about the Matisse IO chiplet capabilities comes from AMD own slides:
https://newsbeezer.com/czechrepubliceng/amd-x570-chipset-and-computex-motherboard/
Pay attention to slides "AMD X570: THE MOST MODERN I/O" and "AMD X570 CHIPSET: FLEXIBILE LANES AND CONFIGS".

X570 has 4 PCIe Lanes for the Processor uplink, 8 dedicated PCIe Lanes and two pairs of 4 PCIe Lanes that can be configured as PCIe or SATA, for a total of 20 PCIe Lanes or 12 and 8 SATA Ports. On top of that, there are also 4 dedicated SATA Ports, 4 USB 2.0, and 8 USB 3.1 10 GBits p/s. This is a quite different arrangement from how it is used in AM4, since we are missing 4 PCIe Lanes, however, we don't know the full list of multiplexed stuff.
Compared to Zeppelin, the Matisse IO chiplet seems to have less PCIe Lanes (Bare minimum 24 to match Socket AM4, we don't know if it has 32 like Zeppelin). However, the extremely interesing stuff is the increased amount of USB Ports. Now you have a total of 12 compared to only 4 in Zeppelin. As I stated before, when using Zeppelin as a SoC, the scarse amount of USB Ports made it hard to use it to drive a consumer computer without a third party USB Controller (Supermicro abused onboard USB Hubs in their EPYC Embedded Motherboards), whereas Matisse IO chiplet can confortably fill that role without help, making it better than Zeppelin. Basically, Zen 2 as a proper SoC suddently makes even more sense...


As things are, we don't know when a Zen 2 based EPYC Embedded would appear, nor what its chiplet composition or full set of exposed features is going to be. Assuming that the Matisse IO die has 32 PCIe Lanes, it could be pin compatible with the first generation of single Zeppelin EPYC Embedded models, at the cost of the new USB Ports. However, there are
EPYC Embedded based on two Zeppelin dies, being functionally equivalent to a 16C ThreadRipper with 64 PCIe Lanes and 2 x 128/144 Bits Memory Controllers. As the Matisse IO chiplet should have been designed with AM4 in mind (Unless AMD likes to waste silicon), a possible 16C Zen 2 EPYC Embedded would actually be identical to the AM4 counterpart (Same IO chiplet, 2 CPU chiplets). Given the fact that the double die EPYC Embedded are nowhere to be found (At least I don't remember ever seeing a Motherboard with them), and that to make a Zen 2 successor AMD should use either a giant Rome IO chiplet or a new ThreadRipper IO chiplet design, chances are that AMD will not directly supercede the double die EPYC Embeddeds with a Zen 2 ThreadRipper level replacement. I don't even think that it can fit in the current PCB size, so it means a new, bigger embedded format not compatible with what they currently use.



Matisse in an embedded format not only seems even better than Zeppelin, it even makes MORE economic sense, given the stupid premium that X570 Motherboards seems to carry. I'm even more confident that we have to get rid of the Chipset in mATX form factors and below.

On a sidenote, I recently saw an EPYC Embedded Motherboard, the AsRock Rack EPYC3251D4I-2T, which is interesing because it has an OCulink Port that can be configured in either PCIe (For NVMe) or 4xSATA mode. SATA Drives are connected via breakout cables like this one. With Matisse IO die two pairs of configurable 4 PCIe Lanes or 4 SATA Ports, you can have two OCulink Ports in a Motherboard and drive either two NVMe Drivers or 8 SATA. While native OCulink NVMe SSDs are not common (If they even exist), you may manage to use them for M.2/U.2 with adapters (However, that adds to the cost. Cables are expensive, too). Regardless, I think that using OCulink with the breakout cable is a superior option to having 4 standard SATA Ports given the fact that you can't use them for PCIe, whereas with an OCulink Port you still have such option.