http://www.ddj.com/hpc-high-pe...ce-computing/216402188
An interesting read. Putting in here because larabee is more a CPU than anything else.
An interesting read. Putting in here because larabee is more a CPU than anything else.
Originally posted by: ilkhan
Actually its a lot of CPUs doing a GPUs work.
And I read that article when it came out on the first when it was linked in GPUs.
Actually its a lot of CPUs doing a GPUs work.
The cores are x86 cores enhanced with vector capability, and the memory system is fully coherent. In short, Larrabee is an enhanced x86 architecture; it supports all the familiar general-purpose programming techniques and tools used on CPUs for decades, and is much like programming a lot of Core i7 cores at once.
Because initial configurations are designed for use as GPUs, they lack chipset features needed to serve as a main CPU running, say, Windows; nonetheless, they are fully capable of running operating systems and general applications. For example, Larrabee, running as a GPU device under Windows, can bring up a BSD OS, with the Larrabee graphics pipeline running as just another BSD application.
Furthermore, each of those Larrabee cores supports multiple hardware threads per core (currently four, although that may change in the future). This is an important part of getting good performance out of the in-order cores; if one thread misses the cache, the other threads can keep the core busy.
A vital component of this is Intel's vectorizing C++ compiler. Developers hate having to write assembly language code, and even dislike writing C++ code using SSE intrinsics, because the programming style is awkward and time-consuming. Few developers can dedicate resources to doing that, whereas Larrabee is easy; the vectorization process can be made automatic and compatible with existing code.
Originally posted by: dmens
of course the *really* interesting details are not in the article.![]()
Originally posted by: Nemesis 1
Originally posted by: IntelUser2000
Originally posted by: Nemesis 1
I corrected you on other thread but Ivy Bridge is a mere shrink of Sandy Bridge. Haswell is the Tock after that and features FMA.
Originally posted by: IntelUser2000
Originally posted by: Nemesis 1
I corrected you on other thread but Ivy Bridge is a mere shrink of Sandy Bridge. Haswell is the Tock after that and features FMA.
Originally posted by: Idontcare
Originally posted by: IntelUser2000
Originally posted by: Nemesis 1
I corrected you on other thread but Ivy Bridge is a mere shrink of Sandy Bridge. Haswell is the Tock after that and features FMA.
Can you expand on your premise for why no FMA in Sandy Bridge precludes Ivy Bridge from having FMA?
Penryn was a mere die shrink of Conroe and yet they shoved SSE4.1 instructions into it.
I haven't seen anything to date that says FMA on Ivy Bridge can't happen or won't happen, outside of your posts that is, so if I am going to discard my vision of the future based on extrapolation of historical events then I'd prefer to do so with something more substantial than faith alone.
Convince me.
Originally posted by: Nemesis 1
Not saying FMA won't happen I just don't believe FMA on Intels or AMDs present backend of their respective cpus cisc well allow for FMa. Check out sun sparc trying to do FMA. It didn't turn out so good.
Actually Haswell would be 3rd generation Sandy so it would be 2 ticks in aroll. As the operands are already in sandy only three active. So its when intel desides to use . It could happen on Ivy bridge. Haswell is not a TOCK. Sandy goes like this Tock tick than another Tick with FMA active. Ivy Bridge =22nm . Haswell= 22nm. FMA and power saving added. I would imagine Intel will do FMA when it suites them . Keeping eye on AMD/ NV/ IBM at same time.Originally posted by: IntelUser2000
Originally posted by: Nemesis 1
I corrected you on other thread but Ivy Bridge is a mere shrink of Sandy Bridge. Haswell is the Tock after that and features FMA.
I just wanted to say hi to you, Vee. You've been missed!Originally posted by: Vee
Originally posted by: dmens
of course the *really* interesting details are not in the article.![]()
Do you mean that there are technical features of interest that the article has omitted? Like it's incomplete?
Or do you mean that the article doesn't delve into the interesting consequences?
Originally posted by: dmens
http://www.ddj.com/hpc-high-pe...ce-computing/216402188
An interesting read. Putting in here because larabee is more a CPU than anything else.
Originally posted by: aigomorla
Originally posted by: dmens
http://www.ddj.com/hpc-high-pe...ce-computing/216402188
An interesting read. Putting in here because larabee is more a CPU than anything else.
enough articles, enough news,
WHERE THE HELL ARE THEY!?!?!?!!?!?
They are so overdue.... And you know it too...
Originally posted by: aigomorla
Originally posted by: dmens
http://www.ddj.com/hpc-high-pe...ce-computing/216402188
An interesting read. Putting in here because larabee is more a CPU than anything else.
enough articles, enough news,
WHERE THE HELL ARE THEY!?!?!?!!?!?
They are so overdue.... And you know it too...
Originally posted by: Vee
Do you mean that there are technical features of interest that the article has omitted? Like it's incomplete?
Or do you mean that the article doesn't delve into the interesting consequences?
Originally posted by: Idontcare
Can you expand on your premise for why no FMA in Sandy Bridge precludes Ivy Bridge from having FMA?
Penryn was a mere die shrink of Conroe and yet they shoved SSE4.1 instructions into it.
I haven't seen anything to date that says FMA on Ivy Bridge can't happen or won't happen, outside of your posts that is, so if I am going to discard my vision of the future based on extrapolation of historical events then I'd prefer to do so with something more substantial than faith alone.
Convince me.
Originally posted by: PlasmaBomb
Originally posted by: aigomorla
Originally posted by: dmens
http://www.ddj.com/hpc-high-pe...ce-computing/216402188
An interesting read. Putting in here because larabee is more a CPU than anything else.
enough articles, enough news,
WHERE THE HELL ARE THEY!?!?!?!!?!?
They are so overdue.... And you know it too...
Your just all hormonal because you want a new toy to play with![]()
Originally posted by: IntelUser2000
Originally posted by: Idontcare
Can you expand on your premise for why no FMA in Sandy Bridge precludes Ivy Bridge from having FMA?
Penryn was a mere die shrink of Conroe and yet they shoved SSE4.1 instructions into it.
I haven't seen anything to date that says FMA on Ivy Bridge can't happen or won't happen, outside of your posts that is, so if I am going to discard my vision of the future based on extrapolation of historical events then I'd prefer to do so with something more substantial than faith alone.
Convince me.
Sure I will. Number 1: http://www.canardpc.com/dossie...Nehalem_a_Haswell.html
Where its basically the only site Ivy Bridge and Haswell is EVER mentioned outside of Intel, and all other sites(like wiki) pulled their data from.
2. Fused Multiply-Add isn't a simple instruction you just slap on like the SSE. It's a big change in the order of adding single cycle SSE. Actually, think of it as adding single cycle SSE on top of a CPU that has absolutely no SSE. Probably more than that which is why only the handful of CPUs support it(Itanium/Power).