9 Layer Vs 8 Layer chips

[MajinVegeta]

With the TBred B core adding a layer to the chip what advantages / disadvantages does this cause?

Granted lower heat/ power requirments is common sence, but what else does it offer or cost?

 

[Eskimo]

Advantages: Easier routing and reduced RC overhead for high speed operation.
Disadvantages: Possible yield degradation, added cycle time, and additional cost.

 

[MadRat]

Do they cut 8 slices of silicon or is there layers of insulation deposited between each layer?

 

[Peacekeeper100]

Actually the layer they are adding is on top. They probably changed around most of the metal layers to take advantage of new routing. Basically the mosfets are created. Then an insulating layer is put on, then a metal layer. The process is repeated until you have the number of metal layers required.

edit- here is a picture. It's not a very good one, but I couldn't find the one I wanted. In both pictures the stuff on top is the metal interconnects. There is an insulator between the metal though. How you make a chip is starting with silicon and the cutting into it(etch) and put other elements in (doping) to get the right effect for the mosfet. After that of the top you add a layer of metal then cut the metal out where you don't want it. Then you add an insulator on top of that. You then cut the insulator where you want the metal to connect to the mosfet. Then add a layer of metal and repeat.

First drawing
Second

What I was looking for
light blue is silicon, dark is most likely silicon oxide (an insulator)

 

[MadRat]

Do layers generally communicate together with direct pathways bewteen layers or are they always connected only through their interconnect along the outside edge?

 

[Eskimo]

There is no general case but both cases exist. Some metal is inlaid within the ILD (inter level dielectric) while other metal makes up a via to another layer. This is one of the advantages of the dual damascene copper process, it reduces the number of process steps necessary and therefore improves cycle time. Nice overview here.

In today's high speed logic devices signals are not routed to pads on the outside of the chip. The delay would be too great for the clockspeeds of today, therefore a process of attaching solder pads directly to the last metal layer is performed. The exact method used to form these connections is relatively proprietary.

 

[rimshaker]

I believe the new Prescott core (P4 on 90nm process) will be using 9 metal layers as well.

 

[Wingznut]

Originally posted by: rimshaker
I believe the new Prescott core (P4 on 90nm process) will be using 9 metal layers as well.

Intel's .09µ process will have seven metal layers, up from the six that .13µ used.


Here's an excellent .pdf on Intel's 90nm process.

 

[rimshaker]

Originally posted by: Wingznut PEZ

Originally posted by: rimshaker
I believe the new Prescott core (P4 on 90nm process) will be using 9 metal layers as well.

Intel's .09µ process will have seven metal layers, up from the six that .13µ used.


Here's an excellent .pdf on Intel's 90nm process.

Oh darn, my mistake, i meant to say the new AMD Tbred 'B' versions now have 9 layers. Was thinking of Prescott for some odd reason. Thanks.