I see some people still not knowing what HT really does on the hardware side,,,
Some are assuming that a with HT on a CPU/core adds onto its 100% speed overal for a second thred, This is false.
A second thred is innitiated with remaining pipelines which may not even be 50% of the core ability, There is also issue that the next few threds trade of available amounts of pipelines which goes into the programming issue (another subject).
HT also requires more memory and bus resources/bandwidth per thred as do all threds HT or pure core power.
Finally you cannot compare C2 vs the I series, Those are 2 completely different archetectures, Its like the Athlon64 vs the P4,,, With the built in MMU and Hypertranport abillity (Intels HT name eludes me at this time, Sorry) opens so much more capability on the I series over C2.
C2 shares the bus to its MMU in the Northbridge, This is loaded up with all data going to and from all hardware expantions and chokes the bandwidth as it loads up, The I series does not suffer this as badly.
Im not sure myself but assume that a 2 core I series w/HT should be at least equal if not better then a C2Q cycle per cycle and same speed memory.
For our lab we have dissabeled HT on most of the servers that do heavy rendering because it just chokes a system to a stall and can issue data out of sequence in some cases, The light load (small thred) systems we leave it on as it lowers latency on request.