Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[Mopetar]

Keeping AM4 + DDR4 alive a little longer in the middle of a DDR5 shortage isn't a terrible idea.

The 6000 series would likely be on AM5 given the information released about the parts. They only list support for DDR5 and LPDDR5, which is a pretty strong indication that it wouldn't be an AM4 part. I also don't think they'd want to pair it with DDR4 either because it would likely significantly hamstring the performance of the souped up GPU that they added.

There will be plenty of left over Zen 3 CPUs that will give people an option and the 5800X3D seems to created specifically to give people on AM4 a solid upgrade path if they're running an older Zen2 or maybe even Zen+ CPU or are specifically looking for a gaming CPU.

 

[DrMrLordX]

The 6000 series would likely be on AM5

I was, of course, referring to a series of Zen3D products rather than anything in the 6000-series.

 

[maddie]

As far as we know, TSMC has stated that stacking is only available on N7. Now, N6 is part of the "N7 family" so it's unclear if it would still be possible on N6, but at face value it isn't. It could come down to simply that N6 is relatively new and TSMC hasn't had time to develop/validate a stacking flow for the process but N7 has been around for a while now so that's what they have ready to use for stacking.

I did see a slide stating stacking for N7/N6 as available now.

 

[Hitman928]

I did see a slide stating stacking for N7/N6 as available now.

Do you have a link? That would answer a question posed here for a while now.

I did find a slide showing off an N5 die stacked with an N6 die but since N5 isn't ready for HVM stacking yet, it doesn't tell us if N6 is available yet or not.

Update on TSMC’s 3D Fabric Technology - Semiwiki

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum. An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link)...

semiwiki.com

 

[moinmoin]

I did see a slide stating stacking for N7/N6 as available now.

There's indeed a slide showing N7/N6 as one. Wasn't aware of that before.

 

[Hitman928]

There's indeed a slide showing N7/N6 as one. Wasn't aware of that before.

Yes, I've seen that too. That was a roadmap they shared last year. I just didn't know what the current status of N6 stacking is as they only seem to have 1 customer who has announced publicly that they are using it and they are using it on N7.

 

[Doug S]

It is interesting they show N3 as being available for top die in 2023 which is the first year it will really be available in quantity anyway. Nothing listed for bottom die, does that mean you'd have to use N5 for that?

Catching up to where the leading edge is might make it interesting for Apple (or I suppose its possible that's the reason why TSMC sped up the timeline for N3) so if they do something with it I'll be curious to see what. Not sure if a multi hundred MB SLC would necessarily be worth it for Apple's market, I think if they did it they'd be more likely to stack two logic dies.

 

[Hitman928]

It is interesting they show N3 as being available for top die in 2023 which is the first year it will really be available in quantity anyway. Nothing listed for bottom die, does that mean you'd have to use N5 for that?

Catching up to where the leading edge is might make it interesting for Apple (or I suppose its possible that's the reason why TSMC sped up the timeline for N3) so if they do something with it I'll be curious to see what. Not sure if a multi hundred MB SLC would necessarily be worth it for Apple's market, I think if they did it they'd be more likely to stack two logic dies.

You'd have to use N5/N7 family for bottom die. Seems to me that this means the top die would have to be flip chip for N3 in 2023 and that having the pad interface for the top die will be ready before the actual TSV option for the backside is ready. I imagine that's the easier part of the process so it makes since that it could be offered sooner.

 

[Thibsie]

That's the hard part. Zen 3 and then V-cache announcement were exciting times. Then they delayed V-cache to Spring and now delivering a gimped version of what they announced. I can't help but feel dismayed.

So, it really was about you.

 

[jamescox]

He is frustrated with AMD's strategy of not trying to expand their desktop market share. The fastest CPU with the best IPC right now is 12900K and soon, it will be the 12900KS. AMD is just sitting still and letting Intel count their bills. We want a bloodbath. But AMD is doing the sensible thing and increasing profits for their shareholders. Good for them but bad for those of us who want excitement in the PC space.

Is intel actually ahead in IPC? I haven’t paid much attention to intel parts; too hot. The definition of IPC implies clock normalized, so if you run both processors at the same clock, does intel still win? I didn’t think so. I thought they were in the lead for some gaming benchmarks by essentially selling an overclocked processor; pushed too far up the frequency curve where the power consumption gets ridiculous. If that is the case, then that implies that intel has lower IPC. If you mean absolute performance, then stop saying “IPC”. IPC seems like it has become a buzzword that a lot of people don’t know the meaning of.

Also, did this false narrative about AMD not caring about the gaming / enthusiast market come from Intel marketing? I used to work at a place where the marketing guys would get on forums to try to stir up discontent or just FUD with the competition. To me, this is the opposite of what is going on. Intel is the one that kept the mainstream market on 4 cores long after it should have been more. I had a 6 core phone before more than 4 went mainstream in PCs. AMD tried to go 8 core with excavator processors and it probably would have worked a lot better if we had managed to move on from DX11 sooner, but Nvidia had reasons to hold that back. Intel has to compete in the enthusiast market because they can only continue to compete in the server and HPC space because AMD is capacity constrained. They are really not even close. I would say Intel is in third place at the moment, I’d you just consider performance and power. AMD and some arm solutions will perform better with better power efficiency.

It is the case that AMD will allocate parts to the server market preferentially, not only because of the money, but also because of the reputation. If a company specs some machines with Epyc and then can’t get the parts, then that is bad. You don’t want your customers questioning why they went with AMD parts. I suspect some of the backlog is due to covid supply chain issues, but everyone needs to deal with that. Preferring to allocate to server parts is a long way from not caring about the non-server market.

With the current situation; we are going to get an essentially gaming specific part on a platform that was supposed to be EOL 2 years ago. That normally would be something that gamers / enthusiast would be really happy about and yet somehow AMD doesn’t care about gamers or enthusiast? The longevity of AM4 has been a huge savings for enthusiast. We are getting Zen4 later this year, so there isn’t much of a reason to bring out a whole product stack. People that already have 5000 series parts probably will want to wait for Zen 4 or even Zen 5 anyway. Is your cpu really too slow for the gpu you have or can get right now? If AM5 is DDR5 only, then they likely wouldn’t bother releasing it right now, even if they could. It would be too difficult to get boards and memory.

 

[igor_kavinski]

Is intel actually ahead in IPC?

Seems so.

I don't disagree with a lot of the other stuff you said in your post.

 

[tamz_msc]

Seems so.

Funny how the tides have turned; Zen used to be particularly good at Cinebench, now with Golden Cove, Intel is disproportionately better at it.

 

[Thibsie]

But how many cores is that? Is this using E cores too?

 

[uzzi38]

But how many cores is that? Is this using E cores too?

It's just a single core.

Golden Cove is just extremely good at Cinebench. Cinebench is still an extremely poor metric for measuring IPC though - it's just a single workload at the end of the day.

I'd still point to SPEC over CB when it comes to IPC.

 

[Det0x]

It's just a single core.

Golden Cove is just extremely good at Cinebench. Cinebench is still an extremely poor metric for measuring IPC though - it's just a single workload at the end of the day.

I'd still point to SPEC over CB when it comes to IPC.

Yes but above chart is without clockspeed being normalized which is required, if you want to compare "IPC"

 

[deasd]

It's just a single core.

Golden Cove is just extremely good at Cinebench. Cinebench is still an extremely poor metric for measuring IPC though - it's just a single workload at the end of the day.

I'd still point to SPEC over CB when it comes to IPC.

GoldenCove good at cinebench but only with R20 and beyond, I already found it has very different result when comes to older ver cinebench like R15

just wonder cinebench just use SSE and never use anything beyond AVX256 or other advanced instructions, R20 could still have a favor to new architecture like ADL/RKL. And I agree SPEC is a better tool.

 

[uzzi38]

GoldenCove good at cinebench but only with R20 and beyond, I already found it has very different result when comes to older ver cinebench like R15

just wonder cinebench just use SSE and never use anything beyond AVX256 or other advanced instructions, R20 could still have a favor to new architecture like ADL/RKL. And I agree SPEC is a better tool.
View attachment 55762

Iirc R20 added AVX2 support. Not sure if R15 used AVX or was just limited to SSE though.

 

[uzzi38]

Yes but above chart is without clockspeed being normalized which is required, if you want to compare "IPC"

Then divide both scores by the max clock rate of each chip if you want (5.2GHz in the case of the 12900K and 5.05GHz in the case of the 5950X). The results will still be mostly the same.

 

[Det0x]

Then divide both scores by the max clock rate of each chip if you want (5.2GHz in the case of the 12900K and 5.05GHz in the case of the 5950X). The results will still be mostly the same.

Do you think 5950x sustain 5050mhz in any workload ? Fit values are way to restrictive at stock.
Indeed values will be ballpart mostly be the same, but for a real "IPC comparison" static normalized cpu clockspeeds are recommend 🙂

*edit*
I think people are mixing together two different terms/metrics.. Singlethread performance is not the same as singlethread IPC (in any given application/benchmark)

 

[coercitiv]

Do you think 5950x sustain 5050mhz in any workload ? Fit values are way to restrictive at stock.

You can consider a lower sustained turbo for the 5950X, even 4900Mhz doesn't change the point that @uzzi38 was trying to make, which is the IPC delta between Golden Cove and Zen3 is significantly smaller in a comprehensive benchmark suite.

The other way we can look at this was the way an AMD rep recently explained it: the IPC gain in Cinebench of Zen3 over Zen2 was 9%, yet the average IPC gain over a comprehensive suite of tests was 19%. Cinebench is a great tool to quickly evaluate (and showcase) the potential of a new chip/architecture, but not a useful tool for an accurate & complete evaluation.

 

[Det0x]

You can consider a lower sustained turbo for the 5950X, even 4900Mhz doesn't change the point that @uzzi38 was trying to make, which is the IPC delta between Golden Cove and Zen3 is significantly smaller in a comprehensive benchmark suite.

The other way we can look at this was the way an AMD rep recently explained it: the IPC gain in Cinebench of Zen3 over Zen2 was 9%, yet the average IPC gain over a comprehensive suite of tests was 19%. Cinebench is a great tool to quickly evaluate (and showcase) the potential of a new chip/architecture, but not a useful tool for an accurate & complete evaluation.

I dont argue against the point he was trying to make, in fact i completely agree with it.. But i think we should try to use the highest level of precision we can, when comparing "hard numbers". 😉

 

[coercitiv]

But i think we should try to use the highest level of precision we can, when comparing hard numbers. 😉

This is the highest level of precision we have, AFAIK we have no clock normalized SPEC numbers.

 

[Thibsie]

It's just a single core.

Golden Cove is just extremely good at Cinebench. Cinebench is still an extremely poor metric for measuring IPC though - it's just a single workload at the end of the day.

I'd still point to SPEC over CB when it comes to IPC.

Very interesting thank you.

 

[Det0x]

This is the highest level of precision we have, AFAIK we have no clock normalized SPEC numbers.

Yes i know, which means we are not comparing "IPC" with that chart, we are only comparing highest singlethreaded performance with it..
As ive said before, it can be a ballpark proxy for "IPC", but everyone should be clear on the difference between these two terms.

 

[Markfw]

Yes i know, which means we are not comparing "IPC" with that chart, we are only comparing highest singlethreaded performance with it..
As ive said before, it can be a ballpark proxy for "IPC", but everyone should be clear on the difference between these two terms.

The other thing, is I saw no power comparisons at any frequency. For example, if a 12900k is done and using 241 watt, vs a 5050x being done at stock (142 watt), who cares what the measuement is, frequency normalized or not. And since wattage is sometimes is what is required for frequency, then for for a non-normalized run its also relevant. In todays world I find it very hard to use that term with any confidence.