Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[Leeea]

What are the chances of this tech appearing in a GPU?

Low in the near term.

GPUs appear to be going multi-chiplet. Probably will have dedicate cache chiplets, with no need to implement stacking technologies.

 

[moinmoin]

Low in the near term.

GPUs appear to be going multi-chiplet. Probably will have dedicate cache chiplets, with no need to implement stacking technologies.

Yeah, the guesses so far were pointing to Infinity Cache being implemented through active bridges/interposers containing cache connecting GPU chiplets, not 3D stacking.

 

[leoneazzurro]

Low in the near term.

GPUs appear to be going multi-chiplet. Probably will have dedicate cache chiplets, with no need to implement stacking technologies.

In reality, rumors point to Navi 31 and 32 using graphic chiplets put directly on the cache chiplets which will work as active bridges. Now, it was said that these packages will be far more complex than Milan-X.

AMD patent outlines GPU with active bridge chiplet design

An important upgrade on a passive bridge chiplet design spotted in previous documents.

hexus.net

Now it's not said that this will be exactly the design used, but the rumors point to a concept similar to this.

 

[maddie]

Yeah, the guesses so far were pointing to Infinity Cache being implemented through active bridges/interposers containing cache connecting GPU chiplets, not 3D stacking.

???????? Confused. Aren't you just arguing semantics? Active silicon on active silicon is certainly 3D stacking.

How are the chiplets stacked on the bridges and if they're active with functioning silicon, how is this not 3D stacking of chips. Using the word "bridges/interposers" does not change the fact.

Another point is that SoIC stacking is almost certainly being used for connecting the GPU chiplets, if only for the >10X reduction in pj/bit of data transfer. Old style microbumps won't work for this.

 

[jamescox]

Same as the normal Ryzens... there's going to be chips that are too leaky to be Epycs.

I find it hard to believe that they are going or fill the whole SKU from salvage alone. The Milan-X parts seem to be basically the same as the F-series parts, which go down to low core count / high clock parts similar to desktop parts.

 

[jamescox]

AMD EPYC 7003 "Milan-X" launches March 21st, specs and pricing leaked - VideoCardz.com

AMD EPYC 7773X 64-core server CPU to cost 8,800 USD The pricing and official specs of the upcoming EPYC 7003 series have been confirmed. The Milan-X series, AMD’s first data-center processors featuring 3D V-Cache, will launch on March 21st. This is the same date that we reported earlier this...

videocardz.com

Videocardz has some updated info on the Milan-X Epycs... all of the models, including the 16 core one are using 8 dies. Interestingly the 16 core model is more expensive than the 24.

That is similar to the F-series parts that are optimized for per core performance; lower core count, but higher cache per core and higher clock speeds. The F-series are 8x1, 8x2, 8x3, and 8x4. They are also a lot higher power consumption. The 32-core is the full 280 W and not all systems support that.

 

[jamescox]

???????? Confused. Aren't you just arguing semantics? Active silicon on active silicon is certainly 3D stacking.

How are the chiplets stacked on the bridges and if they're active with functioning silicon, how is this not 3D stacking of chips. Using the word "bridges/interposers" does not change the fact.

Another point is that SoIC stacking is almost certainly being used for connecting the GPU chiplets, if only for the >10X reduction in pj/bit of data transfer. Old style microbumps won't work for this.

I found that confusing also. I don’t think that we know exactly how AMD’s cache bridge chips will work, but If it is an active bridge chip overlapping (or under lapping) the gpu die, then that is considered 3D stacking. It is only really 2.5D with a passive silicon interposer. I hope that we will get the same infinity cache chips in Bergamo. If they could use 2 infinity cache bridge chips to connect 4 cpu chiplets on each side, then that could be 768 MB to 1 GB of possibly L4 cache. The gpu bridge chips are rumored to be 384 MB or 512 MB, although it is unclear if that is a single die.

 

[moinmoin]

My understanding was that the innovation behind X3D stacking (aside using copper hyper bonding) was TSVs going through several layers (though that's now not used). Classical TSVs usually were just connecting two layers, and with bridges the set of packaging challenges is a very different one. It's possible to share tech there (copper hyper bonding for instance definitely is there to stay), but as the design goals are different that doesn't appear to be worth the effort to me.

 

[MadRat]

I wonder how they will match uneven layers together. They could apply foil layers around stacked components. As you build layers you can bridge over eventually. The adhesives could be a polymer base that allows compressibility that allows an imperfect fit to still be flat at the heatsink. The foils would whisk heat away from the components much better than an inert filler like ceramic.

Then again, you could also just use a single foil layer to bridge heat across the surface and use a rigid cap to sandwich a conductive cementing layer of some kind of polymer between them. Simpler is probably better.

 

[maddie]

My understanding was that the innovation behind X3D stacking (aside using copper hyper bonding) was TSVs going through several layers (though that's now not used). Classical TSVs usually were just connecting two layers, and with bridges the set of packaging challenges is a very different one. It's possible to share tech there (copper hyper bonding for instance definitely is there to stay), but as the design goals are different that doesn't appear to be worth the effort to me.

Tb/s data transfers tell me that you need it.

 

[moinmoin]

Yeah, bumpless copper hyper bonding is a keeper, no question.

 

[Hitman928]

My understanding was that the innovation behind X3D stacking (aside using copper hyper bonding) was TSVs going through several layers (though that's now not used). Classical TSVs usually were just connecting two layers, and with bridges the set of packaging challenges is a very different one. It's possible to share tech there (copper hyper bonding for instance definitely is there to stay), but as the design goals are different that doesn't appear to be worth the effort to me.

I'm not sure what you are describing here. By classical TSVs do you just mean a classical via (which purpose is to connect vertically between layers on the chip)? TSVs have always gone through the bottom substrate to the backside of the chip. Where it connects to inside the chip depends on which TSV technique is used, but via middle seems to be the one the industry has settled on.

 

[Hitman928]

I wonder how they will match uneven layers together. They could apply foil layers around stacked components. As you build layers you can bridge over eventually. The adhesives could be a polymer base that allows compressibility that allows an imperfect fit to still be flat at the heatsink. The foils would whisk heat away from the components much better than an inert filler like ceramic.

Then again, you could also just use a single foil layer to bridge heat across the surface and use a rigid cap to sandwich a conductive cementing layer of some kind of polymer between them. Simpler is probably better.

The wafers are typically around 700 um thick when completed. The layers that are used in stacking will have to be thinned to be a part of the process, so if you need to adjust heights to match heights on a bridged IC, it's not a problem. If you get really complex with multiple layers, then you'll obviously need to make sure you plan accordingly, but you shouldn't have a situation where you have different stack heights unless it's on purpose.

 

[MadRat]

The wafers are typically around 700 um thick when completed. The layers that are used in stacking will have to be thinned to be a part of the process, so if you need to adjust heights to match heights on a bridged IC, it's not a problem. If you get really complex with multiple layers, then you'll obviously need to make sure you plan accordingly, but you shouldn't have a situation where you have different stack heights unless it's on purpose.

Can't just cool 3D cache. So what spans from the substrate to the heatsink?

 

[Hitman928]

Can't just cool 3D cache. So what spans from the substrate to the heatsink?

Solder to the heat spreader and then the heatsink on top of the heatspreader with a little thermal paste (or pad) in between. Just like they do with non-3d cache chips.

 

[MadRat]

Solder to the heat spreader and then the heatsink on top of the heatspreader with a little thermal paste (or pad) in between. Just like they do with non-3d cache chips.

If only it was that simple. If it was solder then no worries about heat because the core would fry and it would never turn on again.

 

[Hitman928]

If only it was that simple. If it was solder then no worries about heat because the core would fry and it would never turn on again.

Maybe I'm misunderstanding the question then, because solder TIM is used by both AMD and Intel on their modern chips between the die and the heatspreader.

Intel Broadens Use of Solder Instead of Thermal Paste for 11th Gen Core Processors - The FPS Review

Intel has become much more generous in regard to utilizing soldered metal rather than thermal paste for improving heat dissipation for its Core processors.

www.thefpsreview.com

 

[maddie]

Can't just cool 3D cache. So what spans from the substrate to the heatsink?

Maybe I'm misunderstanding the question then, because solder TIM is used by both AMD and Intel on their modern chips between the die and the heatspreader.

Intel Broadens Use of Solder Instead of Thermal Paste for 11th Gen Core Processors - The FPS Review

Intel has become much more generous in regard to utilizing soldered metal rather than thermal paste for improving heat dissipation for its Core processors.

www.thefpsreview.com

Maybe he asks this. Lower Cpu die>cache>heatspreader.

3D cache die cover the original L3 area. What's the wattage? ~5 Watts? This is the critical heat load to be transferred to the upper L3 cache die Cu pillar vias and some sort of infill between the via connections. TSMC has a diagram saying much better heat transfer with SoIC direct Cu>Cu bonding. The upper cache die has direct contact with the heatspreader and thus easy to cool.

Here's their slide with the thermal resistance comparison. Can work with low heat flux circuitry.

 

[Hitman928]

Maybe he asks this. Lower Cpu die>cache>heatspreader.

3D cache die cover the original L3 area. What's the wattage? ~5 Watts? This is the critical heat load to be transferred to the upper L3 cache die Cu pillar vias and some sort of infill between the via connections. TSMC has a diagram saying much better heat transfer with SoIC direct Cu>Cu bonding. The upper cache die has direct contact with the heatspreader and thus easy to cool.

Here's their slide with the thermal resistance comparison. Can work with low heat flux circuitry.
View attachment 58995

The stack goes CPU > V-cache > Solder TIM > Heatspreader. The same as a non-Vcache CPU today.

The upper die does not have direct contact with the heatspreader. The V-cache does sit above the normal L3 cache and will cause greater heat buildup in the base L3 cache region, but the L3 cache region should still be less heat density than other parts of the CPU when under load. The FPU region, for instance, will typically have much higher heat density due to both the transistor density and how often the transistors are actually switching.

 

[maddie]

The stack goes CPU > V-cache > Solder TIM > Heatspreader. The same as a non-Vcache CPU today.

The upper die does not have direct contact with the heatspreader. The V-cache does sit above the normal L3 cache and will cause greater heat buildup in the base L3 cache region, but the L3 cache region should still be less heat density than other parts of the CPU when under load. The FPU region, for instance, will typically have much higher heat density due to both the transistor density and how often the transistors are actually switching.

I agree.

I just left out the TIM as it's known to all, or should be, and a constant for all die, 3D cache or not.

 

[nicalandia]

9% higher on MT Geekbench at a lower clock

AMD Ryzen 7 5800X3D 3D V-Cache CPU Benchmarks Leak Out, Up To 9% Faster Than Ryzen 7 5800X

The first benchmarks of AMD's upcoming Ryzen 7 5800X3D, the world's first 3D V-Cache CPU, have leaked out over in the Geekbench database.

wccftech.com

 

[Makaveli]

9% higher on MT Geekbench at a lower clock

AMD Ryzen 7 5800X3D 3D V-Cache CPU Benchmarks Leak Out, Up To 9% Faster Than Ryzen 7 5800X

The first benchmarks of AMD's upcoming Ryzen 7 5800X3D, the world's first 3D V-Cache CPU, have leaked out over in the Geekbench database.

wccftech.com

View attachment 59005

for reference this is what I do on a 5800X PBO tuned!

 

[MadRat]

Apparently they will fill the void with silicon spacers.

I'm surprised that silicon is the solution.

 

[jamescox]

My understanding was that the innovation behind X3D stacking (aside using copper hyper bonding) was TSVs going through several layers (though that's now not used). Classical TSVs usually were just connecting two layers, and with bridges the set of packaging challenges is a very different one. It's possible to share tech there (copper hyper bonding for instance definitely is there to stay), but as the design goals are different that doesn't appear to be worth the effort to me.

It is hybrid bonding, not hyper bonding. TSV stands for Through Silicon Via, so it by definition goes through the silicon substrate. It may not go all of the way to the top of the metal stack on the base die.

 

[jamescox]

Apparently they will fill the void with silicon spacers.

I'm surprised that silicon is the solution.

It uses silicon fillers to fill in the area. It is necessary to use something that matches the thermal expansion rate as the other 2 die as close as possible.