64 bit memory addressing

[Red_Herring]

Hi All,

Could anybody give me an idea or direct me to a resource where I can find how 64 bit memory addresses are translated to access a particular data in main memory.

That is, how a 64 bit memory address is translated to select desired channel,rank, bank, row and column in of the main memory (lets say DDR3 SDRAM) ?

Thank you

 

[Cerb]

They are addressed no different than 32-bit (virtual memory is where the real differences are, between 32-bit and 64-bit). The memory controller, however, does get to decide exactly what address goes where, on a coarse scale (like what range of addresses each DIMM is, and how they are interleaved, for dual-channel access).

http://www.anandtech.com/show/3851/...now-about-sdram-memory-but-were-afraid-to-ask
http://www.es.ele.tue.nl/premadona/files/akesson01.pdf

 

[Red_Herring]

Thank you for your reply.

So, what I understood is, when we say a 64 bit system it refers to a 64 bit virtual memory address (correct me if I am wrong). And this virtual memory is then translated to Physical address from page table and page offset.

Then, how many bits are the physical address that goes to the main memory/controller ? Is it always 32 bit (for both 32 bit and 64 bit system) ?

Thanks.

 

[ikachu]

For AMD chips, it depends on the processor family/model, but for the more recent CPUs it's 40 or 48 bits (depending on the CPU).

You can see a lot of details in the BKDGs:
http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
http://developer.amd.com/wordpress/media/2012/10/48751_BKDG_Fam_16h_Mod_00h-0Fh.pdf

 

[zir_blazer]

http://archive.arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html

 

[Cerb]

Thank you for your reply.

So, what I understood is, when we say a 64 bit system it refers to a 64 bit virtual memory address (correct me if I am wrong). And this virtual memory is then translated to Physical address from page table and page offset.

Then, how many bits are the physical address that goes to the main memory/controller ? Is it always 32 bit (for both 32 bit and 64 bit system) ?

Thanks.

It varies. The PIII could do 36 bits (using PAE), the K8 44 bits (but only 40 external), and I don't think anything is yet past 48 bits. A full 64-bit-wide address space was left undefined for x86-64, as well.

The CPU's registers are 64 bits wide, and addresses are processed as 64 bit integers. However, many of those bits are not used. The memory controller will only use up to what it supports. For example, if the memory controller can support 256GB, it only needs 38 bits. Now, how that goes out to the DIMMs is going to vary. Even a physical address still has to be translated into slot, rank, column, and row(s), and will usually be a chunk of 64*n bits, possibly up to 512b (a typical cache line size).

 

[Red_Herring]

@Cerb: For example, on a DDR3 SDRAM (4GB) we have 240 physical pins. Among them it has 4 bit for chip select S[3:0], 16 bit Address A[15:0] (identifying Row and Column) and 3 bit Bank Address BA[2:0]. That makes it 4+16+3 = 23 bits.

In however bits may the physical addresses have been sent it will eventually be mapped to these pins, in this format. So, what I am trying to understand that, how this mapping is done, lets say, from a 40 bit physical memory address (generated from a 32 bit or 64 bit virtual memory address).

Thanks.

 

[Cerb]

Looking at 8GB DIMM data sheets, I get:
3 canonical (8B wide addressing)
1 chip (more may be used for servers, but not plain UDIMMs)
3 bank
16 row
Up to 12 column

8GB DIMMs all seemed to use at least 10 for the column.

So, that's 33 to 35 bits worth of addressable bytes for 8GB DIMMs.