6 or 8 core Steamroller based AMD CPU likely?

[Erenhardt]

Looking at this page gives the impression that an 8 core steamroller even with added L3 cache would be about the same size as a Kaveri die.

http://www.anandtech.com/show/7507/amd-kaveri-apu-launch-details-desktop-january-14th

AMD said GCN takes 47% of die space. 8 core BD would be about the same size as kaveri.

 

[ShintaiDK]

Remember Kaveri dont have any L3, and the L3 takes up quite some space. And BD/PD dont have any PCIe.

 

[mrmt]

Looking at this page gives the impression that an 8 core steamroller even with added L3 cache would be about the same size as a Kaveri die.

http://www.anandtech.com/show/7507/amd-kaveri-apu-launch-details-desktop-january-14th

OMG 8 anemic cores is so 2011. The problem with this 8C steamroller is that its main market, servers and workstations, is now full of 8C-10C-12C Intel chips, some clocked as high as AMD workstation chips. In other words, while AMD was at least considered in a few cherry picked workloads on that time or could bring bullet points like "moar cores" or "moar threads", they are completely outclassed today. And AMD cannot afford to sell 300+mm^2 dies for peanuts as they are now. This is killing the company.

 

[itsmydamnation]

Remember Kaveri dont have any L3, and the L3 takes up quite some space. And BD/PD dont have any PCIe.

but BD/PD did have a massive amount of Hyper transport, also the L3 arrays themselves didn't take that much space, less then the L2 arrays. So it would just depend on what config amd would go with.

OMG 8 anemic cores is so 2011. The problem with this 8C steamroller is that its main market, servers and workstations, is now full of 8C-10C-12C Intel chips, some clocked as high as AMD workstation chips.

the hyperbole is so frigging anoying, second AMD roll with MCM....

you dont even know the performance profile of SR yet.........

 

[ShintaiDK]

but BD/PD did have a massive amount of Hyper transport, also the L3 arrays themselves didn't take that much space, less then the L2 arrays. So it would just depend on what config amd would go with.

The L3 and supporting infrastructure is anything but small.

 

[itsmydamnation]

im well aware of the PD/PD die, what you have there is a massive amount of I/O (like i said). Not that much L3 array ( like i said) and the memory controller/module arbiter.

the memory controller/arbiter exists in all AMD SOC's. So again where are right back with what i said in the first place...................

 

[mrmt]

the hyperbole is so frigging anoying, second AMD roll with MCM....

you dont even know the performance profile of SR yet.........

FPU and the front end are still shared, they still have only two interger units per "core" and their CMT architecture further complicates cache management. Yes, we know enough to not expect too much of that lemon.