It's pretty big if you believe this: http://assets.vr-zone.net/15272/dieimage.jpg
The amount of effort they are using to push Ultrabooks, there must be more reason than just cost for having only 30% gains despite having GT3.
I beleive it but that must mean they planned to use legacy process node 1Gb parts (60nm or older) for the 1Gb die to be that large.
Even on an older legacy node like 48nm, a 1Gb (128MB) die weighs in at 29mm^2.
Shrunk and produced on a more modern 30 nm or 2x nm process and that 128MB L4 dram cache should be <10mm^2 and silly cheap (<$1).
The reasons not to do it should come down to risk to timeline concerns (package level complexity and interposer validation) and not a question of there being enough space under the IHS. The socket itself would have been designed long long ago to be able to accomodate the interposer footprint if Intel really had plans to bring such a thing to the market.
