45nm Graphics chip on 32nm Clarkdale/Arrandale module

[Idontcare]

http://images.anandtech.com/re...tel/32nmupdate/igp.jpg

Anyone else notice how large that 45nm GPU/IMC is relative to the diesize of 45nm Penryn and even that of the 32nm Clarkdale?

Is Intel's non-larrabee graphics chip really expected to have that many xtors and occupy that large of a die-size when implemented into 45nm silicon?

We know from Nehalem diemaps that Intel's 45nm IMC is not all that large, and that is for triple-channel versus clarkdale is just dual-channel IMC.

So here's the rumor theory for you for the day - what if the GPU on clarkdale/arrandale is actually Larrabee based?

Sure its possible, but is it probable?

I would have assumed integrated Larrabee in Clarkdale was out of the question...until I saw that die-size comparison to clarkdale as well as Penryn. The Anand slides shows the die's in a blurry photochop fashion, here is a clearer shot of the dies in the MCP: http://download.intel.com/pres.../westmere/IMG_5284.JPG

That GPU/IMC must have a ton of xtors in it to be that large relative to Clarkdale, even with clarkdale being 32nm.

 

[phaxmohdem]

Wait, are we talking about the size of the dies, or the size of that guys eyebrows... holy moly

I read somewhere (perhaps even Anandtech) that the GPU on that chip was a 45nm X4500... I would imagine if they had Larrabee up and running, especially along side a 32nm CPU they'd be dying to brag about it.

 

[Idontcare]

Oh lord I didn't even notice, but now that you mention it. :shocked:

I'm OK with the GPU on Clarkdale being non-Larrabee, so if Anandtech says it isn't then it isn't.

I was just surprised at the size of the die, given that it is 45nm so in order to get the die THAT large it must have some serious hundreds of millions of xtors under the hood and I had no idea that Intel's run-of-the-mill oft bashed integrated graphics were that beefy and xtor hungry.

If they aren't...then they only other straw I know of to grasp at is the possibility that Larrabee is about to make a sneak launch and debut as an integrated GPU to every one's surprise.

 

[Nemesis 1]

Well do you think DDR3 would handle say an 8 core larrabee. I would say if we start hearing abour a new memory spec for Sandy. Than maybe well see it than. Sandy is going to need really fast memory also with 256 bit AVX. I just dont see it on core with cpu until faster memory. DDR5

 

[her34]

i think it would be very interesting move if intel put a reduced larrabbee core on Clarkdale/Arrandale for two reasons:

1) using simple gma variant would be wasted silicon for many sytems that use separate gpu. moreso for desktop than laptops

2) it would be a great way of 'sneaking' in a larrabbee core into many computers and thus be a compelling reason for non-game apps to make use of it in same way as cuda(photoshop acceleration, video encoding, etc).

2a) bandwidth isn't as critical for non-game apps

2b) once non-game apps gain larrabbee support, it creates more compelling reason to get full larrabbee gpu rather than nvidia or ati

 

[Idontcare]

Originally posted by: Nemesis 1
Well do you think DDR3 would handle say an 8 core larrabee. I would say if we start hearing abour a new memory spec for Sandy. Than maybe well see it than. Sandy is going to need really fast memory also with 256 bit AVX. I just dont see it on core with cpu until faster memory. DDR5

Nemesis I agree with her34's points. Not thinking larrabee on clarkdale being a super fast graphics solution, it merely needs to be scaled down so as to be good enough to passable for what we all expect from integrated graphics.

Is DDR3 good enough for AMD's, Intel's and Nvidia's current crop of integrated graphics?

You are thinking of integrated graphics done well enough to compete with discreet graphics. That will never happen for TDP reasons alone. QPI takes care of the connectivity to discreet larrabee, pointless to try and bottle that performance under the CPU's IHS.

But for low-performance integrated graphics, wouldn't a much reduced core-count Larrabee be expected to do just fine?

 

[Nemesis 1]

I to agree. But is Intel really that far along. It would be nice. And her34 made some outstanding points.

 

[Idontcare]

Originally posted by: Nemesis 1
I to agree. But is Intel really that far along. It would be nice. And her34 made some outstanding points.

The people who would know also know better than to dare utter a word about it, be it true or false.

But considering they've had 45nm silicon now for 6+ months it wouldn't seem too far-fetched to suspect that in another 6-8 months they will will be ready for release.

Like I mentioned in the OP, I see nothing keeping this from being possible, I just don't know if it is probable.

 

[William Gaatjes]

Originally posted by: Idontcare
http://images.anandtech.com/re...tel/32nmupdate/igp.jpg

Anyone else notice how large that 45nm GPU/IMC is relative to the diesize of 45nm Penryn and even that of the 32nm Clarkdale?

Is Intel's non-larrabee graphics chip really expected to have that many xtors and occupy that large of a die-size when implemented into 45nm silicon?

We know from Nehalem diemaps that Intel's 45nm IMC is not all that large, and that is for triple-channel versus clarkdale is just dual-channel IMC.

So here's the rumor theory for you for the day - what if the GPU on clarkdale/arrandale is actually Larrabee based?
with clarkdale being 32nm.

I am thinking of lot's of L3 cache. maybe combined for larrabee and the main cpu ?
I am purely guessing here...

 

[IntelUser2000]

Sorry to resurrect an old thread but I had to post 🙂.

Here are the die sizes for Intel IGP chipsets:

http://www.intel.com/Assets/PDF/designguide/319972.pdf

G45: 97.848mm2
G35: 124.45mm2
G965: 101.76mm2
945G: 101.76mm2

Process technology scaling isn't perfect and for non memory I'd say its really 0.65x per generation so that puts G45 21% bigger than G35 and G965 54% bigger than 945G at the same process. From the linked picture and from real CPU pic at Intel's site I'd estimate the Clarkdale's Northbridge portion to be 160mm2, which is whooping 150%(2.5x) larger than G45!!

I think Intel tried too hard to not increase die size for their GMCH which sacrificed IGP performance and while its still based off X4500, the drastic increase in die size is a GOOD thing.

From reading about IGPs the Zone Rendering technology on GMA 900/950 worked well when it did and fillrate wasn't the bottleneck in that case(of course ZRT didn't always work but that's not important). Hence why people wondered why some games were slower on X3100 than GMA 950.

The Gen 4 Intel IGPs(X3000/X3100/X3500) I found are actually pretty sensitive to memory bandwidth. It's so much so that I believe the bottleneck is there somewhere related to memory subsystem(In Q3A going from 667 to 800MHz memory gave 10% in high settings). IGPs have something called DMA(Direct Memory Access) which allows to forgo the FSB but its possible most of the transactions are really using the FSB.

With Clarkdale, QPI link having bandwidth of 25.6GB/s will be connecting the CPU and the on-chip Northbridge.

I lost most of the hope for Intel IGPs but the least I don't think the gain won't be as pathetic as G35 to G45 was.

 

[Idontcare]

Originally posted by: IntelUser2000
Sorry to resurrect an old thread but I had to post 🙂.

Here are the die sizes for Intel IGP chipsets:

http://www.intel.com/Assets/PDF/designguide/319972.pdf

G45: 97.848mm2
G35: 124.45mm2
G965: 101.76mm2
945G: 101.76mm2

Process technology scaling isn't perfect and for non memory I'd say its really 0.65x per generation so that puts G45 21% bigger than G35 and G965 54% bigger than 945G at the same process. From the linked picture and from real CPU pic at Intel's site I'd estimate the Clarkdale's Northbridge portion to be 160mm2, which is whooping 150%(2.5x) larger than G45!!

Correct me if I am wrong but it appears that you are attempting to rationalize "xtor budget" of successive IG's by way of leveraging die-size information?

(this is a valid metric, just wanted to make sure I am interpreting the spirit of your post correctly)

So what you really want to say is:

I'd say its really 0.65x per generation so that puts G45 21% more transistors than G35 and G965 54% more transistors than 945G at the same process.

Given that we are apt to associate performance scaling more along the lines of transistor count scaling.

Another thing we are missing here is the clockspeed of the IG. Is it increasing too when they do a shrink?

 

[ilkhan]

well, as long as the thread has been bumped...Do we know if the PCI-E controller is on the northbridge die or the CPU die? Because really, the second die really just the northbridge. memory controller, iGPU, and maybe the PCI-E lanes. Looking at the first picture, Id say the transistor count has to be about even, the CPU die is the smaller one, but its on the smaller process as well. Probably cancels out, or close enough to do so.

Id like to see arrandale with larrabee based graphics (long as we're moving to a new CPU micro-arch might as well change out the GPU too) but I just don't know if thats possible. On the other hand, the power savings from 32nm might allow for extra larrabee cores, too. That's going to be a lot of SKUs, even if there's just 2 levels of GPU performance.

 

[IntelUser2000]

Originally posted by: idontcare

Correct me if I am wrong but it appears that you are attempting to rationalize "xtor budget" of successive IG's by way of leveraging die-size information?

(this is a valid metric, just wanted to make sure I am interpreting the spirit of your post correctly)

So what you really want to say is:
I'd say its really 0.65x per generation so that puts G45 21% more transistors than G35 and G965 54% more transistors than 945G at the same process.


Given that we are apt to associate performance scaling more along the lines of transistor count scaling.

Another thing we are missing here is the clockspeed of the IG. Is it increasing too when they do a shrink?

Yea I guess I am. Transistor counts aren't shown for chipsets but looking at similarity of the circuitry in Graphics MCH scaling should be similar throughout the die. The point of my post is that even with low-end integrated graphics, it takes significant amount of die size and transistors to make it work.

For clock speed its generally an increase but of course not 100% straightforward.

945G: 400MHz core
G965: 667MHz Execution Units(333MHz or 400MHz elsewhere, like TMU and such)
G35: enables full DX10 support, same core clock as G965, 400MHz rest of chip
G45: adds full HD video decoding in graphics hardware, 800MHz EU clock, 400MHz(?) rest of chip
(most people say it only has one clock domain, but some of information I have seen says its not true)

BTW, on whether its Larrabbee of G45 derivative: http://www.hkepc.com/568/page/3#view

It's an older pic based on Havendale, but considering IGP is still same, it looks strikingly similar to G45, and according to most reports it is based on G45.

Originally posted by: ilkhan
well, as long as the thread has been bumped...Do we know if the PCI-E controller is on the northbridge die or the CPU die? Because really, the second die really just the northbridge. memory controller, iGPU, and maybe the PCI-E lanes. Looking at the first picture, Id say the transistor count has to be about even, the CPU die is the smaller one, but its on the smaller process as well. Probably cancels out, or close enough to do so.

Id like to see arrandale with larrabee based graphics (long as we're moving to a new CPU micro-arch might as well change out the GPU too) but I just don't know if thats possible. On the other hand, the power savings from 32nm might allow for extra larrabee cores, too. That's going to be a lot of SKUs, even if there's just 2 levels of GPU performance.

As far as we know the PCI-E controller is with graphics and memory controller.

 

[taltamir]

Originally posted by: Nemesis 1
Well do you think DDR3 would handle say an 8 core larrabee. I would say if we start hearing abour a new memory spec for Sandy. Than maybe well see it than. Sandy is going to need really fast memory also with 256 bit AVX. I just dont see it on core with cpu until faster memory. DDR5

GDDR5 = DDR3
GDDR3 and 4 = DDR2

That is, in design, the GDDR vesions are faster, but mechanically GDDR5 and DDR3 is DDR^3, (aka, apply the DDR "trick" three times)
http://en.wikipedia.org/wiki/P...%28computer_systems%29
So yes, DDR3 can certainly handle a video card.

please forgive inaccuracies in this description as I am grossly oversimplifying the process