Originally posted by: SerpentRoyal
Higher voltage by design?
Micron D9GSV IC's and their successor is similar in Timings to the popular D9GMH chips have, which are also based on the revD die.
Mushkin is the only vendor that is Fabbing this unique IC.
http://www.virtual-hideout.net...B_HP2-6400/index.shtml
http://www.overclock3d.net/rev...c2-6400_4gb_ddr2_kit/1
The difference lies within the density, and the number of banks. This requires more voltage to attain the needed timings. This chip is can hold stock timings from 400 Mhz. thru 533 Mhz.
To make a 2GB module with 16 chips, a 1Gbit chip must be used (1Gbit = 128MB). For 1GB modules with the same number of chips, 512Mbit chips are used. D9GMH is a 512Mbit chip, arranged in 64Mx8, which means each 'cell' is 64Mbits, and there are 8 'cells' per chip. 64*8 = 512Mbit.
To increase the density of the chip, either the number of cells (width) or size of the cells can be increased, or both. If the width is increased, less chips must be used per module.
The total width of the module must be 64 or 128 for desktop memory. Using 16 chips, the 1GB and 2GB sticks in question must both use memory chips that have a width of 8.
The only remaining option to increase the density is to increase the cell size from 64Mbit to 128Mbit. As such, D9GSV is arranged in a 128Mx8 layout.
The 1Gbit chips have a trick up their sleeve though: Double the number of banks.
From Micron's technical documentation:
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent Operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.
In simple terms, DDR2's addressing methods allow multiple memory accesses at once, but only if they are in different banks:
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement - tFAW. This requires no more than four ACTIVE commands may be issued in any given tFAW (MIN) period.
While the tFAW latency restricts the advantages, doubling the number of banks improves memory efficiency a bit. Splitting the data up into more banks increases the probability that two given sets of data are not on the same bank. Thus, a higher probability that when two access are made, the data for each are on different banks. As a result, total access time is reduced, improving latency and effective bandwidth.
Originally posted by: SerpentRoyal
The D9 is CAPABLE of higher voltage and higher core speed. Non-defective D9 should run well at 1.8V/400MHz/4-4-4-12 or 2.1V/500MHz/5-5-5-15.
All quality ICs will run well at low voltage and high core speed with less heat output. The goal is to produce ICs that will run at higher speed with less heat (lower voltage and current).
Intel does not manufacture regular CPU and overclocking higher voltage CPU. The trend in CPU design, of course, is lower VID with higher core speed.
Take a look in history at CPUs. When dual core processors were launched, they were found to be less overclockable than their single core counterparts.
There are a few reasons for this, but the primary reason is that the dual core CPUs have twice the number of transistors.
More transistors means more area, which in turn leads to a higher probability of defects that will limit clock speed.
Memory has the same exact problem, being based off very similar CMOS technology that CPUs use.
For each bit in a DRAM device, there is a transistor and a capacitor.
Every single transistor and capacitor has to be able to switch on and off, as well as drain or charge quickly, or data corruption will occur.
Originally posted by: SerpentRoyal
Do you have any formal training in IC manufacturing and testing?
Yes BS/ME/IEE at University of Michigan and 20+ years of Experience as a Project Quality Manager in Automotive, and Aerospace Electromechanical Devices.
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