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256bit DDR-2

We have had 256bit DDR-2 on graphics cards for what? 2 years now? More?

Why isnt anyone developing a 256bit DIMM and 256bit memory controller? Wouldnt this absolutely destroy Dual Channel DDR2 and Rambus XDR in raw bandwidth?

I know it would be a lot of traces on the motherboard, adding layers and cost... but it would satisfy even the most bandwidth hungry CPU with a single dimm, simplify the memory controller, and have a lot of headroom for scaling with future CPUs.

I can see in AMDs case why it hasnt happened, they would need a new A64 stepping just to support it. On the Intel boat though a proprietary memory controller could easily be developed by any of the chipset makers. Although i could see there being standards conflicts im sure the memory makers would love to stay with 256bit DDR-2 as well (over rambus or other emerging technologies).
 
too many traces needed for it
a lot more complexity in the bridge(intel) or processor(amd)
and absolutely no performance gain...

Josh
 
Originally posted by: SocrPlyr
too many traces needed for it
a lot more complexity in the bridge(intel) or processor(amd)
and absolutely no performance gain...

Josh

I would argue less complexity in the bridge, no need for dual channel controllers anymore.

No performance gain from double the bandwidth at low latency?
 
Originally posted by: ribbon13
That 256-bit memory on memory cards is exactly that... dual channel / quad channel

So you are suggesting that one DDR/DDR2/GDDR3 chip actually has 4 memory controllers that access the single chip.

That doesnt make much sense as we dont call dual channel memory 128bit on motherboards.
 
Originally posted by: Acanthus
Originally posted by: ribbon13
That 256-bit memory on memory cards is exactly that... dual channel / quad channel

So you are suggesting that one DDR/DDR2/GDDR3 chip actually has 4 memory controllers that access the single chip.

That doesnt make much sense as we dont call dual channel memory 128bit on motherboards.

The way the memory is installed onto the video cards allos for it to be "256 bit", its an architecture, the memory itself isn't 256bit, its just the way its configured and accessed on the board.
 
So does anyone have a diagram of how this works? it is my understanding that the 144pin FBGA packaging on samsungs GDDR3 and DDR2 was 256 bit natively.
 
Originally posted by: Acanthus
So does anyone have a diagram of how this works? it is my understanding that the 144pin FBGA packaging on samsungs GDDR3 and DDR2 was 256 bit natively.

I don't know about DDR2 or GDDR3, but DDR is 64 bit and they just add channels. So for a 256 bit bus they'd split the RAM between four 64 bit controllers.
 
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