Technically the hypertransport bus isn't even involved in memory transfers, since the CPU has the memory controller and a direct path to memory. However if any of the data has to be measured including the HTT path, to be determined by the benchmark apps, that could result in differences.
What you may be running into is the result of the differences in transfer cycles. If you run two busses out of sync, not 1:1, then you end up with one or the other often having to "wait" a clock tick or two or 3 for the other one to be ready for a data transfer. Even though one might be ready "more often" because of a higher frequency, it still isn't ready at exactly the same time. Running things at a ratio of like 2:1 can eliminate some of that, since it's always exactly the same number of cycles difference, but at that point you have lost a lot of the pure bandwidth on one side so it's still slower.
Running the busses at different speeds can still result in higher performance, if it allows one of them to reach massively higher speeds. For instance P4's got to much higher bus speeds than the memory speeds could keep up, and it was still faster to have them at that bus speed than to have them synced with the memory. But if you've only got a difference of a few megahertz, it's better to maintain sync.