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1Gig vs. 2Gig Cache

BAHAHAHA!!! I almost choked on my food when I saw 1GIG vs 2 GIG cahche!!! BAHAHAHAH!!!

1'st off, it's 1 MEG vs 2 MEG. Second, It's not 1 Meg vs 2 Meg, it's actually 2x 512kb vs 2x 1024kb. Now will it make a difference, yes but very small.
 
There was a misprint in one of my schoolbooks that said Itaniums had 32GB of cache...

Cache is one of those things that I thing certain applications will be better able to take advantage of than others. Gaming performance shouldn't be all that much better with 2X1Mb cache over 2X512Kb.

 
In this particular situation, there was not a sufficient ammount of understanding on the subject for a question, much less a poll. Either way, cache sizes are of minimull gain past 1MB imo.
 
It all depends on the application, how it's written, etc.

I remember when I moved from a 256 KB cache PIII to a *slightly* faster PIII with 512 KB cache. At the time I was working on a program that did a lot of image resizing with ~300 KB files. The performance DOUBLED! Mostly because the image data fit in the larger cache of the newer CPU. For pretty much everything else, the performance increase was minimal.
 
Originally posted by: Shenkoa
In this particular situation, there was not a sufficient ammount of understanding on the subject for a question, much less a poll. Either way, cache sizes are of minimull gain past 1MB imo.

Do you think that applies to all processor architectures? The deeper pipeline PIV's have more L2 cache to keep the pipelines fed don't they? AMD's shallower pipeline kind of negates the huge L2 caches I agree. It is a question not a criticism!
 
Originally posted by: michaelpatrick33
Originally posted by: Shenkoa
In this particular situation, there was not a sufficient ammount of understanding on the subject for a question, much less a poll. Either way, cache sizes are of minimull gain past 1MB imo.

Do you think that applies to all processor architectures? The deeper pipeline PIV's have more L2 cache to keep the pipelines fed don't they? AMD's shallower pipeline kind of negates the huge L2 caches I agree. It is a question not a criticism!

Intel also uses the Larger L2 cache's because of the FSB that they use. The larger L2 cache helps to eleminate the latencies and help out the slower interface (i think).

And yea, the AMD chips don't really need that much cache (as Intel ones) thanks to their architechture not being THAT hungry, and also thanks to the on-die controller and Hypertransport interface. (i think)
 
I think that applies to what a basic users needs are. If your browsing the net, checking email and playing games. I dont think you would notice a difference no matter the architecture.

Maybe if it was an advanced user who does imaging or movie editing.
 
For playing games the cache shouldn't matter too much because the game developers would have optimized out a section of code that would significantly slow down a machine.

So unless you are using a cache that is noticably smaller then what the average is, or is noticably smaller then what the required chip for the game has, you shouldn't notice too much of a difference.

I still like the idea of having more Cache though. So any time I go shopping for a chip I make sure it has a bunch.
 
All depends on how the program is coded. Apparently FEAR gets a nice boost from going from 512k of cache to a meg (per core).

Generally speaking, however, AMD does not benefit from larger cache sizes as much as Intel does because AMD's onboard memory controller gives it better memory bandwidth, with lower latency.

Intel needs a large cache due to the slower/higher latency memory controller. And Intel can afford to have larger caches because they're already one manufacturing process ahead, at 65nm.
 
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