128 Bit CPUs

[Tuna-Fish]

It's like people wondering how long IPv6 will last, since we ran out of IPv4 addresses in a few decades. The difference is that IPv4 gives less than one unique IP address per person on earth. IPv6 could assign 4 billion unique addresses to every person on Earth. Or, to think of it another way, with IPv6 you could break the Earth up into 2^64 pieces of ~240 grams each, and assign a unique IP to each one.

Umm, no. IPv6 doesn't have 64-bit addresses -- it has 128-bit addresses. The present idea seems to be that each individual isp customer should be granted a /64.

 

[LiuKangBakinPie]

4.2 billion + IPV6 adresses

A very looooooooooooooooooooooooooooooooooooooooong time

 

[MrTeal]

Umm, no. IPv6 doesn't have 64-bit addresses -- it has 128-bit addresses. The present idea seems to be that each individual isp customer should be granted a /64.

Heh, oops. I should have looked that up. Too much talk of 64 bits, I guess.

 

[bryanW1995]

128-bit memory addressing is absolutely absurd.

256-bit memory addressing is even worse. At that point, you may be dealing with more bits of RAM than there are elementary particles in the universe.

No way, we just need to find some "elementary-er" particles...

17 billion GB of memory is probably a ways off. How long did it take us to go from 4kb to 4 gb? Can we agree that it was approximately 25 years? This jump in capacity will be 17,000 times greater than that one. Even making extremely optimistic assumptions, it should take us 30+ years to get there, and I wouldn't be surprised at all if it actually takes closer to 100 years.

 

[taltamir]

In terms of addressing, you're not going to be seeing 128bit CPUs ever.

The reason? Physical size.

A 128 bit number is on the order of 10^38.

The number of atoms in a carat of diamond is 10^22.

The difference is 10^16.

Since a carat weights 0.2 grams, doing the math you get about 200 billion kilos (or 440 million tons) of diamond for which you can address every atom of it.

Considering modern battleships weigh in the 50k tons, you're looking at addressing the atoms of 9 thousand of them. Give or take a few.

Good luck multiplexing all those address lines.

Just wait until I build my moon sized super computer!

Sandybridge has AVX which can process 256-bits of data so does that make it 256-bits???

I do believe you are correct, sir.

 

[Blitzvogel]

I know a bunch of navy people who would be willing to classify the Zumwalt-class destroyer as a BB. The consensus seems to be that it's called a DD only because BB's are presently the butt of the joke about following the old paradigm too long, when everyone should have been building aircraft carriers instead.

It's only 15k tons, which is a far cry from the Iowa, but it's still heavier than many of the Pre-DN battleships. It's certainly not a destroyer, because DD's are traditionally used for killing small ships, submarines and aircraft, each of them a task that the Zumwalt does not do. Instead, Zumwalt is meant for engaging surface and ground targets with missiles and guns. It only has 2 guns, but they are water-cooled, fully automated and have fire rates good enough that it can land as many projectiles per minute on the target as the Iowa. The projectiles themselves are, of course, much lighter.

Are any of the Zumwalt's even in construction yet? Even still, I would think of them as being like current current multi-mission surface ships. Yes, there is a focus on land attack, but even with guns, they still have missiles, and I guess they could be considered modern battleships, though realistically, modern cruisers could be too, despite the lack of guns being the main armament.

When I mentioned "battleship", I mean in the traditional sense, with a wide dreadnought derived hull, three or more 12"+ multigun turrents, and sh!t loads of armor including torpedo blisters.

 

[Blitzvogel]

What was interesting about the EE? It was just another typical RISC based FLOP monster, like every other design out there. Not smart, just wide. And the VU's were essentially T&L units, just on the cpu instead of the gpu. VU0 wasn't terribly fast, but was extremely flexible (more so than the DirectX 8.1 level hardware the Xbox was sporting), VU1 was quite fast but not very flexible (probably closer to the fixed function T&L unit of the geforce 2). And from what I remember, the two were difficult (or nearly impossible?) to use together. Still, at the time, the VU0's performance about matched the fastest non-fixed function T&L hardware available (sega's boards used in Virtua Fighter 4), and the VU1 about matched the Geforce 2, while at the same time the fillrate and bandwidth of the PS2's gpu was on par with the Radeon 9700 Pro that wouldn't be launched until a few years later. I'd imagine the two systems were separated more in performance by software support than hardware, because the PS2 was fairly beefy in quite a few individual areas, just the sum of the parts didn't seem to work out.

I think the PS2's worse curse was the lack of a proper 3D GPU, but then again, the EE was built around providing the geometry.....

The other curse was the lack of TMUs, which meant forced multipassing.

The third curse was the 32 MB of RAM, which probably wasn't enough, even with the insanely fast eDRAM.

Yes, the PS2 was an insanely flexible machine, but overall lacked the brute strength of the Xbox. The PS3 really is the logical descendent of the PS2, with a continued push on a very flexible vector-ish-centric silicon via the Cell, including using it for graphics, but providing the system with a real 3D GPU.

 

[IHateMyJob2004]

128 bit processing compared to 32 bit and 64 bit processing

So, you want more floating point precision? 10^19 meg of memmory allocation not sufficient?

 

[lamedude]

I do just so we can finally put x87 out to pasture.

 

[LiuKangBakinPie]

The reason that 128-bit CPUs exist today has to do with integers and complex math. That level of accuracy simply isn't required in day to day computation. Perhaps in quantum computing or for powering time machines, I don't know. I have a feeling that, at some point, we are going to start mapping atoms. If something like the replicator in Star Trek ever exists we'll probably need 128-bit CPUs.

 

[cytg111]

..and I wouldn't be surprised at all if it actually takes closer to 100 years.

I guess thats a pretty safe guesstimate i guess(tm).... unless, of course, you're into the whole cryogenics + offsprings shebang.

 

[tweakboy]

Your a good guy,,,, 120 I say the rear 400 watt hercik ah for your house. things sound amazing now but whats fool is all the wire work my dad did tought me,

Do yourself a favor and buy some Klipsch 5.1 system, one of the lights well put on your forehead, for epreve anti cocd hmmmmmmmmmmmmmmmmm

 

[Idontcare]

Your a good guy,,,, 120 I say the rear 400 watt hercik ah for your house. things sound amazing now but whats fool is all the wire work my dad did tought me,

Do yourself a favor and buy some Klipsch 5.1 system, one of the lights well put on your forehead, for epreve anti cocd hmmmmmmmmmmmmmmmmm

I feel like you just broke your own previous world record here. :hmm:

Not really sure what is an appropriate response to commemorate such an event - is this a

type event, or is this more of a D: achievement?

 

[taltamir]

I guess thats a pretty safe guesstimate i guess(tm).... unless, of course, you're into the whole cryogenics + offsprings shebang.

It is actually called Cryonics, the preservation of humans via freezing.

Cryogenics is the generation of very low temperatures (for physics applications)

Hollywood never gets it right.

Also, what is the "offsprings shebang" exactly?

 

[hanspeter]

Good luck multiplexing all those address lines.

So you want as many address lines as there are combinations of those bits?

 

[Schmide]

So you want as many address lines as there are combinations of those bits?

How else do you figure to address something?

At every level there is some sort of bank of address lines as well as the possible logic at leach level to multiplex those branches.

 

[gorydetails]

These bit have to go somewhere,,,

 

[Anarchist420]

I have a pretty relevant question. How can the Dreamcast's CPU only be 1.4 GFLOPs where the EE is 6.2 GFLOPs? Doesn't the PS2 have 2 64 bit vector units and the DC has 1 128 bit wide vector unit with the PS2 not even being double the clock speed of the DC?

None of that generation's consoles had very good graphics, but then neither does this one since not all games have AA. Few games had AA in the DC/GC/PS2/Xbox generation and even when DC games used AA it was ordered grid which sucked, rather than rotated grid. The fact that so few games of that era used mipmapping also made them look like shit. The gamecube's low precision RGBA back buffer made artifacts really apparent.

The strengths of the PS2 were its CPU and that it could use RGBA8 for the back buffer and RGB8 for the front buffer and could even do 32 bit Zbuffer (although the PS2 did use a low internal res). The Xbox was the best HW wise (still didn't have rgms and didn't have high pixel shader precision though), and the GC was the worst in terms of feature set (low precision frame buffer, high S3TC ratio, limited GPU programmability that the CPU couldn't make up for, small storage size) although it was more efficient than the PS2. The other thing that sucked with that generation was the 60Hz refresh rate on CRTs became apparent.

 

[Cerb]

I have a pretty relevant question. How can the Dreamcast's CPU only be 1.4 GFLOPs where the EE is 6.2 GFLOPs? Doesn't the PS2 have 2 64 bit vector units and the DC has 1 128 bit wide vector unit with the PS2 not even being double the clock speed of the DC?

Well, no, both had 128-bit vector units, and both had two of them that did FP. Note that, like the Cell, Toshiba and Sony did not bother with sustained calculation rate specifications. Meanwhile, Hitachi gave both burst (1.4 GFLOP @ 200MHz) and sustained (<1GFLOP for the DC's CPU, I believe), and that processor was pretty straight-forward, unlike the EE. The SH-4 variant Sega used had specs that could fairly compared against PC CPU specs.

That said, a naive look at the EE gets me to 3.6 GFLOPS (1 FPU + 5 VU0 + 6 VU1). There may be some in-cache-only parallelism exploitable via the VU design, which is weird, such as maybe counting simultaneous read/writes to caches and memory (32-bit regs, 16-bit regs, 2 local caches, multiple external buses/links), which would be impractical for anything but a specialized test program. There may be graphics processing tricks that can be used for more general calculations included, too. The EE is about as simple as our medical regulations.

 

[Anarchist420]

Well, no, both had 128-bit vector units, and both had two of them that did FP. Note that, like the Cell, Toshiba and Sony did not bother with sustained calculation rate specifications. Meanwhile, Hitachi gave both burst (1.4 GFLOP @ 200MHz) and sustained (<1GFLOP for the DC's CPU, I believe), and that processor was pretty straight-forward, unlike the EE. The SH-4 variant Sega used had specs that could fairly compared against PC CPU specs.

That said, a naive look at the EE gets me to 3.6 GFLOPS (1 FPU + 5 VU0 + 6 VU1). There may be some in-cache-only parallelism exploitable via the VU design, which is weird, such as maybe counting simultaneous read/writes to caches and memory (32-bit regs, 16-bit regs, 2 local caches, multiple external buses/links), which would be impractical for anything but a specialized test program. There may be graphics processing tricks that can be used for more general calculations included, too. The EE is about as simple as our medical regulations.

Thanks for answering my question

 

[Dark Shroud]

To over simplify both Sandy Bridge & Bulldozer are technically 256bit CPUs.

 

[spurious_ai]

No, they are 64-bit CPU's

There is not a 128 bit or 256 bit ALU in the processor. It is for marketing and an easy way to represent the instructions to programmers.

A 128 bit SSE,2,3,4 "register" can represent 16 8 bit integers, 8 16-bit integers, 4 32-bit integers, 2 64-bit integers, 4 32-bit floats or 2 64-bit floats. Note that 128-bit integer is missing.

The proof is found in the bit shift instructions. You can shift left or shift right any of the above integer formats, but there is not an instruction to do the shifts on the full 128-bits. There is an instruction that lets you left shift the bytes that is available in the erroneously named _mm_slli_128 intrinsic (PSLLDQ).

Another glaring error is the absence of the ROL, ROR and NOR instructions.

Shifting a 128-bit integer requires 5 SSE instructions instead of 1.

I can't blame them for this choice. The bit shifting is the only area where they would really need a 128-bit ALU. Even if it took more cycles they should have instructions for 128 and 256-bit shifts.

 

[jumpncrash]

Screw 128-bit I want zettabyte's of memory bandwidth, twelve hundred million trillion a-sexual stream processors that multiply and a self aware CPU capable of infinity operations per second.

If terminator taught us anything it's that self aware processors are a bad thing

 

[Markbnj]

There's no one measure of the bitness of a processor. Back in the day, the definition used to be the maximum precision math the cpu could do (so bulldozer and sandy bridge would be 256-bit cpus), but now it's generally the amount of addressable memory (so bulldozer and sandy bridge are 64-bit).

You're right that the definition is a little ambiguous to people like me who don't design chips, but I would say that the designations 16-bit, 32-bit, and 64-bit have historically referred to the width of the registers and the memory address bus. Registers are used for holding data, instructions, and memory addresses. In order to work with a 64-bit wide memory address bus, the registers that hold addresses had to be 64-bit.