【der8auer】Threadripper 2990X Preview - aka EPYC 7601 overclocking

[dacostafilipe]

There's a follow-up video : https://www.youtube.com/watch?v=yiHscW5Scfc

The interesting part is at the end where he tests Epyc in multiple configurations (8ch vs 4ch).

 

[beginner99]

There's a follow-up video : https://www.youtube.com/watch?v=yiHscW5Scfc

The interesting part is at the end where he tests Epyc in multiple configurations (8ch vs 4ch).

And what are the conclusions?

 

[dacostafilipe]

And what are the conclusions?

"Real world performance seems not to be really affected" ... "Infinity fabric will work really well" ...

With Cinebench (!) the difference between 8ch and 4ch is really slim: 5790 vs 5750

I still think that there will certainly be cases where this configuration will bottleneck performance, but he seems kinda optimistic.

 

[TheGiant]

Any CFD calculation benchmarks with 4ch vs 8ch?

thanks

 

[LightningZ71]

Theoretically, the resulting bandwidth will be roughly the same no matter where the 4 channels are connected. The main issue is, and has always been latency. If you have a task that thrashes the local L3 heavily and makes a LOT of memory read requests, it's going to be impacted by the latency of distant memory requests. For tasks that tend to be very bandwidth sensitive, that tends not to be the case (yes, there are outliers) as they are most interested in getting blocks of memory quickly.

Where this will likely be most noticeable, outside of synthetic benchmarks that zero in on the issue, is in games that are very system latency sensitive. I imagine that TR2 will still have some sort of gaming mode just as TR1 had to address those situations, though, it rarely made a huge difference when the software didn't have a basic compatibility issue.

 

[StefanR5R]

I'm not sure, did anybody post a link to ServeTheHome's EPYC memory scaling test yet?

"AMD EPYC Naples Memory Population Performance Impact"
By Patrick Kennedy - July 31, 2018
https://www.servethehome.com/amd-epyc-naples-memory-population-performance-impact-at-16-cores/

Summary:

• 1, 2, 4, 8 DIMMs were tested with EPYC 7301 (16 cores).
• It is implied that the 4 DIMMs config was populated such that there was 1 DIMM per die. A config with 2 DIMMs on 2 dies + 0 DIMMs on the other 2 dies was presumably not tested.
  
• STREAM triad scales super-linearly due to NUMA effects.
• Linux kernel compile and 7zip compression tests have almost double the performance when going from 1 DIMM to two, 13...20 % higher performance when going from 2 to 4, and only single digit % gain when going from 4 to 8.
• C-Ray rendering performance is not influenced by the number of DIMMs at all.

The virtually non-existing gain in real-world applications when going from 4 to 8 DIMMs is not surprising, given that merely a 16 core CPU was tested here.

 

[PeterScott]

Do think it's going to be 12 and 16 cores with two active dies (same as TR1); and then the 24 and 32 core models with 2+2+0+0. Rewiring it to work 1+1+1+1 (if it's even possible) sounds like way too much work for such a low volume product.

The ideal solution of course would be to make Threadripper models with SP3, and just disable ECC to segment out.. which is pretty much what Intel is doing with the Super HEDT.

Gamers Nexus seems to be confirming that 32 core models are using a 2+2+0+0 Memory Controller config.
https://youtu.be/D8CRg-eWRn0?t=5m14s

 

[csbin]

2990WX@5.1Ghz（LN2）

https://www.tomshardware.com/news/amd-threadripper_2-vs-intel-core_x,37550.html