Recent content by Tuna-Fish

9999X3D priced at $999?

Is MALL gone and folded into L2? It's not listed. That's a huge hole in the lineup between a 18GB 64CU model and the 36GB 154CU one.

That's because MALL/performance is a completely nonsense thing that doesn't matter! You do not need a specific amount of MALL for specific amount of performance. You need a specific amount of MALL for a given target render resolution. It doesn't matter how complex your scene is or how much time...

... If it hits 6.5, we know that 6.5 wasn't the target because for the past decade AMD has set unrealistically high frequency targets that they always miss? If it only gets 6GHz, then maybe 6.5 is the target. The part I'm annoyed with is that half the internet is going "omg 7GHz AMD wins...

I'd just remind everyone again that 7GHz is supposedly the frequency target, and that AMD has set very aggressive frequency targets (which they then miss) for the entirety of Lisa Su's tenure. If the result is 6.5GHz, 7GHz was probably the target.

Clear Linux did it's purpose, the optimizations in it mostly made into other distros. It doesn't have to keep going.

Yeah, that's fair. But that's not what MS uses to make decisions about the future -- right now, they are losing the market. They might feel compelled to do something to change the situation. That something might be to get out of the hardware business. Or it might be to launch a new console...

Xbox is not doing just fine. Their sales are cratering, and iirc PS5 is outselling them >4 to 1. If MS wants to stay in the game, they probably want a new console fairly soon to reset the situation, then Sony has to respond not too long after or they risk having something much more powerful...

I think you are both massively overestimating what compute can do for you. For a true doubling, they don't need to just add another int pipeline, they'd need to double all the memory access related resources. At which point the units would be twice the size and there would be no point. The...

VL is "vector length". And it's not a command, it's an extension. Without it, all AVX-512 instructions operate on ZMM (512-bit) registers. It allows using XMM (128-bit) and YMM (256-bit) registers instead.

They are currently using an outsourced memory controller IP where a single controller handles 128 bits, or 4 DDR5 channels (which, for historical reasons, are also called 2 channels). Presumably, they are switching to a different memory controller IP, that handles 64 bits, or one dimm's worth...

Cadence announced yesterday that they taped out a combined LPDDR5/LPDDR6 controller. Given how different the standards are, that's a weird product.

The CPUs wouldn't be that much faster than they were back then, even if they could run at absurd frequencies today. The P4 was fundamentally pretty bad at hiding memory latency and getting memory-level parallelism. Memory latency has not gone down much at all. Even if all computational...

In zen3, the slab is between the heatsink and the compute, vidya probably doesn't want the frequency regression.

144MB, 240MB if dual stacked. 48MB on die with the cores, 96MB per v-cache die.