Recent content by LightningZ71

After seeing some of the recent leaks on the whole bLLC setup. I'm honestly less impressed. If true, the 8+16 CCDs just double their L3 from 3MB per core to 6. While that is certainly a lot, it's not as impressive as going from 4MB to 12MB for the X3D cache chips. It'll certainly help...

If you truly believe that Strix Halo really costs north of $600 per unit from a COGS standpoint, then yes. The absolute cheapest trash bin level laptops with near give away level processors are being sold new at near $300, and this thing is quite a bit better equipped than 99% of those, even if...

From what we know, it's the same cores and the same node. There shouldn't be much of a difference in non bandwidth limited scenarios.

Early adopters get squeezed for high margins?!?! This has never ever happened before in the history of history!

The sad part is that they aren't just late, they aren't even eventually fixing the yields on many of their older nodes. Instead of figuring out and rectifying what went wrong, they seem to just stumble along into the next node (or half step), which flops, and only mature previous nodes a few...

Well, at one point, the rumor mill had great divergence between consumer CCDs and server CCDs, to the point that all mobile and mainstream desktop parts were going to have the cut down mobile Zen5 core AVX-512 implementation and only Threadripper and server would have the full thing.

At one point, Intel was practically giving away i3-1005g1 chips. You could barely find any reasonably priced i7 products, but I3 parts were sold for barely more than the cost of the rest of the notebook components...

I wonder if they will increase the downstream link bandwidth to the chipset? 4 x PCIe 4.0 is a bit slow at the moment. 4 x PCIe 6.0 would keep pin count low while quadrupling bandwidth and would be manageable as it's all inside the board. If they could then give us 4-8 more exposed lanes...

The chip is called a PLX switch. There's one embedded inside of each motherboard chipset on b650/x670 etc boards already. It's how you get from 4 lanes coming from the cpu to the many lanes and devices hung off of them. There are dedicated PCIe cards that have them, from 4 lanes to dual m.2 4...

Lest we forget, even if 18A was this spectacular node, Intel doesn't have anywhere near the capacity to feed the market, and would likely struggle to handle their own internal needs on top of any customer of significant size with even perfect yields on the process for a long time. They also...

Cache is king: dual bLLC Nova lake rumors https://videocardz.com/newz/amd-ryzen-dual-x3d-and-intel-nova-lake-dual-bllc-leaks-surface-almost-simultaneously Video Cardz Article

As I suggested the last three times this product came up, it should have been called a 4XXX series EPYC model. That's where it'll see the biggest gains, server and workstation class workloads.

At the time, I had a close friend working at a local white box computer shop that was able to get it at cost, but it did take some doing. That thing lasted me for a long time.

Intel is in a similar position today with Arrow Lake vs. Raptor Lake as they were in the Willamette days. People like to forget that Pentium III -S Tualatin existed. Official specs topped out at 1.4 Ghz with a 133Mhz FSB, but it was trivial on decent boards to get an FSB of 150Mhz and an...

On their own, in a idle-but-doing-userland-stuff-too no. For ANY of this to work, there needs to be a "low power island" where LP cores live, where they are all etched with high density, low leakage transistors and have a low power uncore that they share. This has to be separate from the high...