- Mar 3, 2017
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Ignoring the video, I'm pretty sure I saw a Twitter leak earlier of a 32 CU version...can't remember the number of cores, but frankly, 16 cores for every Strix Halo sounds wasteful compared to typical AMD.Frankly, the existence of the 128-bit "LP" model there puts this whole slide under doubt. That one doesn't make any sense in the slightest, that's just simply far too cut down.
That one implies to me that MLID was told something about "LP" with regards to Strix Halo from an OEM or someone else, and assumed it meant there would be a significantly cut down model, and just made up the specs (by just halving everything).
While we don't speculate on rumors, we confirmed this ourselves by digging through Google's cache. Sure enough, as the image above from Google highlights, it lists a newly unannounced model of Ryzen mobile processor. Under the listing via the product compare section for the ASUS Vivobook S 16 OLED (M5606) notebook, it is listed with the AMD Ryzen AI 9 HX 170, which appears to be one of AMD's upcoming Zen 5-based mobile chips codenamed Strix Point.
Yea.Is that so?
Consult the ThinkPad T14 pdf pleaseJust like you knew about the naming scheme and weren't proven wrong the very next day.
Yea.Is that so?
Consult the ThinkPad T14 pdf pleaseJust like you knew about the naming scheme and weren't proven wrong the very next day.
The Zen5 improves 10% relative to the Zen4 IPC, and >10% in the CR23 1T test. Also, Win10 enthusiasts, please note that starting with Strix Point, AMD will not be providing Win10 drivers.
The fact that this guy is a product manager at Lenovo has some credibility to me.10% would mean AMD messed up the design really bad. I very much doubt this is true.
The fact that this guy is a product manager at Lenovo has some credibility to me.
Slide apparently comes from older presentation:
View attachment 98568
I mean... even the lowest preliminary Geekbench score leak ST % increase was higher than that at iso clock. If we would speak about MT scores at same core number in power limited situation, I will believe for sure. We are basically at the same process node.I don't buy it at all. For a wider grounds-up major redesign that would be a f*** up of Bulldozer proportions. Never ever are 10% true...I hope... xD
Lion Cove is "supposed" to be 33% wider decode with more than 2x uop capability and also an expansion for both FP, ALU, and L/S units for a typical 20% increase but with a widely rumored clock decrease.I don't buy it at all. For a wider grounds-up major redesign that would be a f*** up of Bulldozer proportions. Never ever are 10% true...I hope... xD
Lion Cove is "supposed" to be 33% wider decode with more than 2x uop capability and also an expansion for both FP, ALU, and L/S units for a typical 20% increase but with a widely rumored clock decrease.
Maybe both AMD/Intel will deliver massive 40%+ gains but maybe they are both ~10%.
Without knowing the details(meaning insider information) high level descriptions can only provide us with very limited information on what it is actually capable of. Both Prescott and Bulldozer looked promising, until it wasnt.
Competitors tend to be also closer to easier other than expected since the leader relaxes a bit to maximize financial gains while the lagger does better due to the natural tendency of people to work harder in times of distress.
Users of both camps expect massive, sweeping wins that will completely obfuscate the other but it happens few, and far between.
Intel has higher clocks, so them achieving 20% uarch gain but with lower clocks resulting in overall 10% gains and AMD having 10% gains is really the same thing.The quote is that Zen 5 IPC is only a 10% increase. . .
Intel has higher clocks, so them achieving 20% uarch gain but with lower clocks resulting in overall 10% gains and AMD having 10% gains is really the same thing.
Remember when they got 25% overall gains confused with ~10-15% uarch gain and rest in clocks for Zen 4? I don't really see anyone complaining.
"Looking ahead, we are very excited about our next-gen Turin family of EPYC processors featuring our Zen 5 core," said Lisa Su, chief executive officer of AMD, at the conference call with analysts and investors (via SeekingAlpha). "We are widely sampling Turin, and the silicon is looking great. In the cloud, the significant performance and efficiency increases of Turin position us well to capture an even larger share of both first and third-party workloads."
It actually gets worse because TOPs requirements is going up soon. Nutella is single-handledly ruining multiple generations of SoCs.
Is he?The fact that this guy is a product manager at Lenovo has some credibility to me.
Frankly, the existence of the 128-bit "LP" model there puts this whole slide under doubt. That one doesn't make any sense in the slightest, that's just simply far too cut down.
That one implies to me that MLID was told something about "LP" with regards to Strix Halo from an OEM or someone else, and assumed it meant there would be a significantly cut down model, and just made up the specs (by just halving everything).
From that article:Anyone has a semiaccurate subscription ?
No, it means Charlie is deranged."Microsoft is pushing ‘AI’ not to benefit the users but to offload some very expensive costs from their datacenters to the user."
Could this mean less sales for nVidia of AI related HW to datacenters going forward, since (part of) the work will be done on client PCs instead?
The Zen5 improves 10% relative to the Zen4 IPC, and >10% in the CR23 1T test. Also, Win10 enthusiasts, please note that starting with Strix Point, AMD will not be providing Win10 drivers.