Zilinx ISE

[scaryjeff]

As part of my degree, we are about to start using this software which apparently is used to design microprocessors. I was just wondering if this software is used in industry at all, or whether it's just a rubbish student program. In particular does anybody use this software at work? Sorry if this is in the wrong forum, but it did seem to be pretty technical.

 

[blahblah99]

I use the whole Xilinx software suite along with ModelSim. It's a pretty complete solution that'll allow you to synthesize vhdl files, place pinouts (and contraints), and generate the programming file. Once you figure out the bugs and workarounds with ISE, it's a great software. However, it's interface with ModelSim is HORRIBLE.

At work, we had code for a spartan fpga that was writtened and synthesized on ISE 3.1. Well, I have the newest 6.1i version, and unfortunately, Xilinx changed so much between 3.1 and 6.1 that the original code wouldn't synthesize anymore, so I had to go through some of the top level vhdl files and fix it to get it to synthesize correctly. Once it synthesized, I went and simulated the fpga with ModelSim and I didn't like it all due to the poor interface between the two.

Our fpga is a 100k gate part, with 10 block rams. My revised FPGA code to enable more functionality in the project uses about 90k of gates, 9 block rams, and all 4 global clock buffers, with the majority of the modules optimized, so we are really pushing the FPGA to its limit.

You're pretty much limited to Xilinx, Altera, or Lattice. Each company has their own version of software. I've also used Lattice briefly and found that to be much friendlier.

 

[CTho9305]

edit: never mind. misread your post.

 

[Matthias99]

I used the Xilinx software and ModelSim as well in an EE class on circuit design (we got to play with some of their FPGAs while learning VHDL). As was mentioned, while the programs all seemed okay on their own, we had to jump through *way* too many hoops to actually get from VHDL to something we could do timing sims on to something that could actually be loaded into the arrays.

We used *much* smaller FPGAs, and wrote very simple designs, but apparently it scales well. The impression I got from my professor was that it *was* used in the real world -- and, obviously, in academic settings as well.

 

[scaryjeff]

Okay, thanks guys I hope that I will be able to acheive something with the software.

 

[CTho9305]

Maybe I'm missing something, or modelsim is just better with verilog. I write my verilog, start up modelsim, type "vlog foo.v", "vsim foo", then set up my waveforms as I want, and type "run -all". I haven't tried to use modelsim to put stuff onto FPGAs - we did that using some Altera tools.

 

[blahblah99]

Originally posted by: CTho9305
Maybe I'm missing something, or modelsim is just better with verilog. I write my verilog, start up modelsim, type "vlog foo.v", "vsim foo", then set up my waveforms as I want, and type "run -all". I haven't tried to use modelsim to put stuff onto FPGAs - we did that using some Altera tools.

I dont' like ModelSim at all because it's not intuitive. It works, but it's not intuitive. For example, the way I simulate my vhdl code is to write it up in ISE, synthesize it, add a waveform bench waveform. I then add my signals, 0's, and 1's. Then in ISE, I click "Launch ModelSim simulator". The program does its thing and pops out the result. Great. Everything good so far. Now lets say I want to add another input to the module. I modify my vhdl, recompile, and hit Launch Simulator again. The program throws a fit because there's already one instance open - I have to close the old one in order to re-simulate the recompiled code.

Why can't it be like Orcad Capture/Pspice where you modify a schematic, hit simulate, and the program automatically re-simulates without having to manually close pspice?

I'm sure there's a better way to do this, but for average users like me, they just want simulated results without having to restart the program everytime.

This is just an example of the clunkiness that is inherent to ISE and ModelSim. I can speak of a lot more. I'm not bashing Xilinx's software, they did a great job on putting together a package that'll allow designers to shrink their developement time, but the software could use a little facelift.

 

[CTho9305]

I write my verilog in xemacs, save, then recompile & resimulate in ModelSim.

 

[AbsolutDealage]

Yes, we use both Xilinx and Modelsim out here.

 

[scaryjeff]

What do you mean by 'out here'?

 

[mAdD INDIAN]

Does anyone in the industry use Altera Quartus? We use that in our second year Digital Systems course.

It has a nice interface, but has issues with managing different compiliations in one project. and when you add external files into the project, it won't copy them in the directory of the project, which needs to be done if you are re-using the symbol.

Minor issues, but sometimes cause problems when your in a rush.

 

[AbsolutDealage]

Originally posted by: scaryjeff
What do you mean by 'out here'?

Nothing really... just meant that our company uses the tools in question.