- Sep 18, 2011
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Don't forget custom ARM/RISC-V efforts...
Phytium's
CAS's
Alibaba's/T-head's
Bottom two being open-source means less risk in implementing them in custom SoCs. Not including the China's SiFive (StarFive) which can license SiFive cores to customers in China.
RISC-V has the benefit of somewhat having implementations exploring GPGPU implementations: ThinkSilicon's RISC-V NEOX;
"(If) the main CPU is also RISC-V based, it is possible to dynamically off-load the main CPU of some tasks making some of the GPU cores appear as additional system cores"
Basically, offloading VPU tasks to the GPU with homogeneous instruction-set(RVV extentsion when RVVX/RVVG isn't in use). If the workload isn't GPU-related or needed, then get extra deep VPU little-cores.
Phytium's D2000 can already do some x86/x86-64 tasks via Box86(~80% native)/Box64(~90% native)+wine.
In general, Zhaoxin is largely limited to Linux anyway. With most optimizations going towards Linux/Android for the Zhaoxin first post-S3 DX12 graphics. Which I believe is the goal going forward; to get Zhaoxin into x86/ARM handhelds, so VIA can re-brand them and distribute them.
Phytium's
Xiaomi - Microarchitectures - Phytium - WikiChip
Xiaomi is an ARM microarchitecture designed in-house by Phytium for their consumer market and server-based microprocessors.
en.wikichip.org
CAS's
GitHub - OpenXiangShan/XiangShan: Open-source high-performance RISC-V processor
Open-source high-performance RISC-V processor. Contribute to OpenXiangShan/XiangShan development by creating an account on GitHub.
github.com
Alibaba's/T-head's
Hot Chips 2020 Live Blog: Alibaba Xuantie-910 RISC-V CPU (3:00pm PT)
www.anandtech.com
GitHub - T-head-Semi/openc910: OpenXuantie - OpenC910 Core
OpenXuantie - OpenC910 Core. Contribute to T-head-Semi/openc910 development by creating an account on GitHub.
github.com
Bottom two being open-source means less risk in implementing them in custom SoCs. Not including the China's SiFive (StarFive) which can license SiFive cores to customers in China.
RISC-V has the benefit of somewhat having implementations exploring GPGPU implementations: ThinkSilicon's RISC-V NEOX;
"(If) the main CPU is also RISC-V based, it is possible to dynamically off-load the main CPU of some tasks making some of the GPU cores appear as additional system cores"
Basically, offloading VPU tasks to the GPU with homogeneous instruction-set(RVV extentsion when RVVX/RVVG isn't in use). If the workload isn't GPU-related or needed, then get extra deep VPU little-cores.
Phytium's D2000 can already do some x86/x86-64 tasks via Box86(~80% native)/Box64(~90% native)+wine.
In general, Zhaoxin is largely limited to Linux anyway. With most optimizations going towards Linux/Android for the Zhaoxin first post-S3 DX12 graphics. Which I believe is the goal going forward; to get Zhaoxin into x86/ARM handhelds, so VIA can re-brand them and distribute them.
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