Hi,
I'm looking at the Genoa-X EPYC 9684X as an example, and I can't figure out what is the maximum bandwidth of communications between cores and between CCD's.
First, the GMI3 slides talk about 36 Gb/s per interface to the I/O die (and there is one such interface in the above mentioned chip), while this post shows a single CCD can even get to ~70GB/sec read from memory, so that is almost 16 times higher than the GMI3 number. So what is true?
Second, what does the server I/O die allow when it comes to CCD to CCD communications? I couldn't find what topology the network is (all connected? mesh? ring?) and what capacity it can supply, and what is the bisection bandwidth.
Regards,
Ilan
I'm looking at the Genoa-X EPYC 9684X as an example, and I can't figure out what is the maximum bandwidth of communications between cores and between CCD's.
First, the GMI3 slides talk about 36 Gb/s per interface to the I/O die (and there is one such interface in the above mentioned chip), while this post shows a single CCD can even get to ~70GB/sec read from memory, so that is almost 16 times higher than the GMI3 number. So what is true?
Second, what does the server I/O die allow when it comes to CCD to CCD communications? I couldn't find what topology the network is (all connected? mesh? ring?) and what capacity it can supply, and what is the bisection bandwidth.
Regards,
Ilan
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