- Mar 3, 2017
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Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.
Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.
Siena has 32 zen4/zen5 cores at most (it goes to 64 Zen4C/Zen5C cores but I doubt AMD wants to put low-clock low-cache C cores on threadripper) , even tr 5995wx had more cores and memory channels than this. The most likely scenario is that Threadripper will be on the SP5 socketThat's not the rumour. SP6/Sienna is 6 ch, SP5/Genoa is 12 ch, those are known. Threadripper so far always has been re-using the server platform, but in case of non-Pro with cut channels. So the rumour went with 8 ch and 4 ch, a cut of a third of the respective server channels.
Anyway as @SteinFG mentioned before AMD already publicly announced unifying both Pro and non-Pro before, so an uncut SP6/Sienna based TR seems most likely at this point.
DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR
DESIGN. BUILD. ACCELERATE. ON THE ULTIMATE WORKSTATION PROCESSOR AMD launched the AMD Ryzen™ Threadripper™ line of disruptive, high performance desktop processors in 2017. Since then, Threadripper processors have quickly become the processor and compute platform of choice for the world’s most...community.amd.com
You missed my point entirely, it's about powaaah NUCs 😅You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.
Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.
In addition, the "why" of Siena, discussed with press afterwards, is to have something that reasonably fits a 1U chassis and into the same set of TDPs that Intel used for a decade, so that customers who want to keep all their infrastructure can replace old server blades 1-to-1.Siena is SP6 socket platform. Pretty much everything that's known:
Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.
The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.
That's... Exactly what I was saying:Except that AMD making everything dual CCD would (excluding the IO die) double the cost of making the chip while they would only be able to make half as many. I don’t think they will consider that route.
because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
Lol! I wouldn't upgrade my 5900x system on any AM5 based product if that was the case (may not anyway, but that's a budget issue). The main reason I use a 12- core system is that I have VMs running at times that use as many as 6 cores (6c/12t). Though, if the Zen6 HD CCD matched or exceeded the performance of the Zen3 core, which is certainly possible, I would rethink things.Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.
The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.
You didn't mention NUCs anywhere, you only said you could ditch your desktop with It.You missed my point entirely, it's about powaaah NUCs 😅
Noooooo, you got bit by Nosta 😭There could be a mild refresh of the branding for AMD's products that reflects the change in structure and warrants a pricing increase...
8950X 2 X Zen5 CCD 8 cores each, 16/32 Costs $A
8955X 1 X Zen5 CCD, 8 cores 1 X Zen5c CCD 16 cores, 24/48 Costs $A + $75
8900X 2 X Zen5 CCD 6 cores each, 12/24 Costs $B
8905X 1 X Zen5 CCD 6 cores 1 X Zen5c CCD 16 cores, 22/44 Costs $B + $70
8800X 1 X Zen5 CCD, 8 cores, 8/16, Costs $C
8805X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 12 cores (faulty cores) 20/40 Costs $C + $70
8700X 1 X Zen5 CCD 8 cores, reduced power, 8/16 Costs $D
8705X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 8 cores, Reduced power (bad CCX) 16/32 Costs $D + $70
8600X 1 X Zen5 CCD 6 cores, 6/12, Costs $E
8605X 1 X Zen5 CCD 6 cores, 1 X Zen5C CCD 6 cores (bad CCX and a bad core) 12/24 Costs $E + $60
It also allows a new Suffix
8900V 1 X Zen5C CCD, 16 cores, 16/32 Costs $X
8800V 1 X Zen5C CCD, 12 cores, 12/24 Costs $Y
8700V 1 X Zen5C CCD, 8 cores, 8/16 Costs $Z
So, there's a way if the WANT to. They just have to CHOOSE to do it.
And, no, I don't think that they will actually do ANY of the above for the 8000 series...
Noooooo, you got bit by Nosta 😭
I don't think this is much of a problem. From a practical standpoint, the lower end of the lineup is targeted towards primarily consumers (gamers, office PCs, etc.). 8 full cores has generally been sufficient for that market. The ones who need more MT performance are content creators and professionals, and it wouldn't be a stretch to upsell them to the higher tiers.Amd already mixes CCDs with different amounts of cache on each die (7900X3D, 32MB and 96MB), so I think there's no barriers for them to just do the same with Zen5 chiplet and Zen5c chiplet.
The problem is - it only raises core counts for Ryzen 9, because R7 should stay as 1 ccd, so it'll have at most 8 Zen5 cores.
The lineup will look like this:
R9 8+16
R9 6+12
R7 8
R5 6
Doesn't really work, so I think amd will just wait until Zen6 with its 16C Zen6 ccd.
Ironically DLSS just hallucinates it anyway 😂I have no DLSS which would generate this missing information.![]()
The only weird design I have identified is a ultra-high-frequency Zen5 concept. Which pushes the OoO-logic into the front-end with a full-on trace cache. Opting for a ultra-modern ROB-free checkpoint-based retire. Which from the model numbers might go for a 9Fx5(F going into core count for change in max cores) number denotation if the concept launches. Only the UHF and Standard HF designs are appearing on N3=45CPP.Only if the new "V" models are fabbed on GloFo FDSOI.
Ironically DLSS just hallucinates it anyway 😂

Mmmpf.But back to Zen5.
I would like to see a CCD with both standard and dense cores.
Smaller CCD: 4x Zen5 + 4x Zen4/5c
Bigger CCD: 6x Zen5 + 6x Zen4/5c
With this, they can have the full lineup:
CPU 1: 3x Zen5 + 3x Zen4/5c -> 6C12T
CPU 2: 4x Zen5 + 4x Zen4/5c -> 8C16T
CPU 3: 5x Zen5 + 5x Zen4/5c -> 10C20T
CPU 4: 6x Zen5 + 6x Zen4/5c -> 12C24T
CPU 5: 2xCCD 8x Zen5 + 8x Zen4/5c -> 16C32T
CPU 6: 2xCCD 10x Zen5 + 10x Zen4/5c -> 20C40T
CPU 7: 2xCCD 12x Zen5 + 12x Zen4/5c -> 24C48T
If they made only a single CCD then I would go with 4x Zen5 + 6x Zen4/5c instead for a total of 20C40T.
In mobile and desktop you would lose a lot of ST performance by using only C cores, that's not something users want.Mmmpf.
Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?
Especially if V cache stacking can balance out the L3 difference in the dense CCDs.
Stacking the cache requires that you build in vias into the L3 area of the chip. This causes a density hit and would force the C core CCDs to be larger than they currently are. You might see this in the future, but, I doubt it any time soon.Mmmpf.
Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?
Especially if V cache stacking can balance out the L3 difference in the dense CCDs.
Great minds think alike:I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.
Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.
It is the obvious play if AMD want more MT perf in desktop. Even if some people get really confused at the ideaGreat minds think alike:
Mmmm with Intel spamming e-cores, it doesn't matter. Back to 'more is better'.I don't think this is much of a problem. From a practical standpoint, the lower end of the lineup is targeted towards primarily consumers (gamers, office PCs, etc.). 8 full cores has generally been sufficient for that market. The ones who need more MT performance are content creators and professionals, and it wouldn't be a stretch to upsell them to the higher tiers.
But not the frequency deficit.Mmmpf.
Nobody seems to think that they could employ pure Zen(n)c based SKUs for higher core counts?
Especially if V cache stacking can balance out the L3 difference in the dense CCDs.
There could be a mild refresh of the branding for AMD's products that reflects the change in structure and warrants a pricing increase...
8950X 2 X Zen5 CCD 8 cores each, 16/32 Costs $A
8955X 1 X Zen5 CCD, 8 cores 1 X Zen5c CCD 16 cores, 24/48 Costs $A + $75
8900X 2 X Zen5 CCD 6 cores each, 12/24 Costs $B
8905X 1 X Zen5 CCD 6 cores 1 X Zen5c CCD 16 cores, 22/44 Costs $B + $70
8800X 1 X Zen5 CCD, 8 cores, 8/16, Costs $C
8805X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 12 cores (faulty cores) 20/40 Costs $C + $70
8700X 1 X Zen5 CCD 8 cores, reduced power, 8/16 Costs $D
8705X 1 X Zen5 CCD 8 cores, 1 X Zen5C CCD 8 cores, Reduced power (bad CCX) 16/32 Costs $D + $70
8600X 1 X Zen5 CCD 6 cores, 6/12, Costs $E
8605X 1 X Zen5 CCD 6 cores, 1 X Zen5C CCD 6 cores (bad CCX and a bad core) 12/24 Costs $E + $60
It also allows a new Suffix
8900V 1 X Zen5C CCD, 16 cores, 16/32 Costs $X
8800V 1 X Zen5C CCD, 12 cores, 12/24 Costs $Y
8700V 1 X Zen5C CCD, 8 cores, 8/16 Costs $Z
So, there's a way if the WANT to. They just have to CHOOSE to do it.
And, no, I don't think that they will actually do ANY of the above for the 8000 series...
Mmmm with Intel spamming e-cores, it doesn't matter. Back to 'more is better'.
The only problem is price IMO
I don’t know the numbers for N5, and I am too lazy to do the math, but on 7nm each CCD costed like $70-$80.
