Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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A///

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Feb 24, 2017
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They'll figure it out eventually. Thermal density is definitely a big problem, especially on newer nodes, but that's the kind of raw engineering problem that engineers love. Maybe they'll flip the stacking or something else, but I doubt V-cache will always come with such a penalty.

Eh, he kinda sidesteps it a little. And the raw technical merit of such a product is very clear. It's not going to happen for the Zen 4 gen, but Zen 5, Zen 6? I think that interview will not age particularly well, and is more targeted in the "selling the products we have today" sense.

May be something on am6 with zen 6.
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Exist50

Platinum Member
Aug 18, 2016
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???????????????????????????????????????????????????????????????????????????????????????
I assume Zen 6 will reuse the AM5 socket. But even if they don't, they're not going to move the mainstream off 2ch for cost reasons, nor provision that many extra pins in the socket to support both. Just to steal a pinout from Igor's ARL leak, look how many pins even 2ch takes.

1689803427048.png
 

A///

Diamond Member
Feb 24, 2017
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I assume Zen 6 will reuse the AM5 socket. But even if they don't, they're not going to move the mainstream off 2ch for cost reasons, nor provision that many extra pins in the socket to support both. Just to steal a pinout from Igor's ARL leak, look how many pins even 2ch takes.

View attachment 83277
this is all true and I agree with you with the grand exception of zen 6 being on am5. why i say this? amd is bound to take one big step and mess it all up. by then intel will e on their 2nd new ceo after pat, this ceo being a tuna fish or octopus,
 

Ajay

Lifer
Jan 8, 2001
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Eh, he kinda sidesteps it a little. And the raw technical merit of such a product is very clear. It's not going to happen for the Zen 4 gen, but Zen 5, Zen 6? I think that interview will not age particularly well, and is more targeted in the "selling the products we have today" sense.
I think, by what he says, it *won't* be Zen5. Obviously, AMD didn't do it with Zen4 - so he's not talking about that. The point of 'E' cores is Area optimized cores vs performance optimized cores. Personally, I don't see the need for this on the desktop. The current CCD-IOD system offers the flexibility AMD needs for Desktop parts. # of active cores and frequency/voltage/power limits can be set by OEM in the BIOS to get the product that they need for desktop. Mobile is a different story. Servers may be a different story - depending on what customers want (AMD could very easily provide some selective CPUs with a mix of CCDs with performance and high density cores on the same package). I don't see the benefit of having one HP CCD and one HD CCD on the desktop. IMHO.
 
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Joe NYC

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Jun 26, 2021
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Not according to a recent TPU interview with David McAfee



There are 2 ways to interpret it - that hybrid means different instructions sets or different types of cores.

AMD is not going to pair CPUs that differ in the instructions they support. We will see about the other part / other interpretation.
 

Ajay

Lifer
Jan 8, 2001
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There are 2 ways to interpret it - that hybrid means different instructions sets or different types of cores.

AMD is not going to pair CPUs that differ in the instructions they support. We will see about the other part / other interpretation.
He does say no to different ISAs or different IPCs. So, again, I’m confident that it’s a no for Zen5 and likely no for Zen6. But, as always, we shall see. All bets are off for AM6.
 

eek2121

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Aug 2, 2005
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Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels

The chances of AMD releasing 4 memory channel socket are near zero.

What could be interesting, if Strix Halo can fit into AM5 socket, would be to have 4 internal memory channels and 2 external.
Disclosure: I have you on blocked (so your posts aren't shown unless I am suckered into clicking the show hidden button) because you at one point posted a ton of nonsense, but occasionally something somewhat intelligent wanders from your keyboard to this forum, and I usually find out by others NOT ignoring you..so here we go:

While I understand the argument, I'm gonna have to disagree here.

You know what happened when you plugged 2 memory sticks into a 1950X? You had dual channel memory. It wasn't like you gimped your machine by NOT having 4 sticks, 4 sticks just performed faster. Just like 2 sticks/dual channel on a 7950x will perform better than 1 stick/one channel. Your system won't refuse to boot, or even operate poorly, if you only have 1 stick of RAM. It will just operate more slowly. No. The REAL reason is that AMD doesn't want to add all those extra traces/wiring (which I suspect they can do without a socket change, but I could be mistaken) and the extra bandwidth, however, ignoring that....DDR5 IS ENOUGH for 24-32 cores. AMD would sooner sell me a bridge than convince me otherwise.

...even if bandwidth were an issue, AMD could save money and up core counts by releasing a 4hi+8lo chiplet and using that in place of the single chiplet offerings.

Atom in raptor lake is (mostly) just a 4 core cluster sharing a single 'big' core's resources. Food for thought.

...oh and in case some new person to this forum thinks I'm an Intel fan? Look at my post history. Also please note that my household consists of 7 AMD machines and zero Intel machines (fun fact: I also have 3 RISC-V machines and 7 non-mobile ARM machines...and a bunch of Apple products that aren't listed here)
 

moinmoin

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Jun 1, 2017
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Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels

The chances of AMD releasing 4 memory channel socket are near zero.
I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).
 

eek2121

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Aug 2, 2005
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I wonder if it occurred to the VideoCardz guy that the chip might be 12 “Zen 5” cores.

A bit of a ramble:

A lot of people are speculating that AMD will go hybrid on Zen 5, but IIRC Zen 5 work began prior to Intel publicly announcing their efforts. I am not saying this is the case, but I feel like AMD would “play it safe” by introducing a hybrid design with an existing architecture first. I will admit, however that there are some indications that AMD is pursuing a hybrid design for at least some chips.

I guess we will find out in January.

If they go hybrid for desktop, it will be interesting to see if they stick with chiplets since having multiple core designs/configs complicates the design. They would either have to move to 2 CCDs per chiplet or come up with another approach unless they are segregating server from the rest. Any thoughts on this?
 

Timorous

Golden Member
Oct 27, 2008
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I wonder if it occurred to the VideoCardz guy that the chip might be 12 “Zen 5” cores.

A bit of a ramble:

A lot of people are speculating that AMD will go hybrid on Zen 5, but IIRC Zen 5 work began prior to Intel publicly announcing their efforts. I am not saying this is the case, but I feel like AMD would “play it safe” by introducing a hybrid design with an existing architecture first. I will admit, however that there are some indications that AMD is pursuing a hybrid design for at least some chips.

I guess we will find out in January.

If they go hybrid for desktop, it will be interesting to see if they stick with chiplets since having multiple core designs/configs complicates the design. They would either have to move to 2 CCDs per chiplet or come up with another approach unless they are segregating server from the rest. Any thoughts on this?

For desktop use dense cores and normal cores.

X950 could be 8 normal and 16 dense.
X900 could be 8 normal and 12 dense.
X800 could be 8 normal and 8 normal.
X600 could be 6 normal and 6 normal.

Obviously there can also be 3d variants as well.

This would be a large core count uplift but with Intel going 6p 8e on RPL-R and going with even more e-cores in future products I think AMD may have no real choice but to increase core counts something like the above to stay competitive in Mt and productivity workloads at each tier.
 

uzzi38

Platinum Member
Oct 16, 2019
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@eek2121 Just FYI, but the 7540U ships in a configuration that screams the rumoured PHX2 specs, but currently ships with PHX1.

2 Zen 4 cores that can boost to advertised boost frequency, 4 Zen 4 cores that are capped to 3.8GHz for single thread loads, and when the entire chip is stressed they drop to 2.9GHz.

Seems fairly clear that the rumoured 2+4 design is almost certainly on point. So effectively the low end will migrate from 4 cores to a 2+4 design. Doesn't seem like a stretch to believe that 8 core designs will migrate to 4+8 really.

Only remaining question is: but what about gaming laptops. Will the 4+8 design be optimal, or will there need to be another pproach instead?
 

soresu

Diamond Member
Dec 19, 2014
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I wonder if it occurred to the VideoCardz guy that the chip might be 12 “Zen 5” cores.

A bit of a ramble:

A lot of people are speculating that AMD will go hybrid on Zen 5, but IIRC Zen 5 work began prior to Intel publicly announcing their efforts. I am not saying this is the case, but I feel like AMD would “play it safe” by introducing a hybrid design with an existing architecture first. I will admit, however that there are some indications that AMD is pursuing a hybrid design for at least some chips.

I guess we will find out in January.

If they go hybrid for desktop, it will be interesting to see if they stick with chiplets since having multiple core designs/configs complicates the design. They would either have to move to 2 CCDs per chiplet or come up with another approach unless they are segregating server from the rest. Any thoughts on this?
I'm more interested in the rumored 'Sarlak' variant with up to 40 RDNA3 CUs.

With something that meaty I could probably just ditch my desktop for all but work related use cases.
 
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SteinFG

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Dec 29, 2021
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I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).
Just want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.

I'm more interested in the cores: if TR on Siena ever comes out, will it use 64x Zen4c or 32x Zen4? 4-channel or 6-channel ?
 
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SteinFG

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Dec 29, 2021
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Looked at amd's statement again - seems like Siena TR will not come out:

"Threadripper processors have always been a platform that is defined by leadership performance and capability which enables unlimited creative potential. Examining what our most demanding enthusiasts and content creators value most in the platform has led us to unify the Threadripper and Threadripper PRO product lines. Going forward, the Threadripper platform will now use a single "common infrastructure." This means there will be one set of Threadripper PRO processors to choose from, with one CPU socket and chipset, and every processor will be based on AMD Ryzen Threadripper PRO silicon"
 

Ajay

Lifer
Jan 8, 2001
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Just want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.

I'm more interested in the cores: if TR on Siena ever comes out, will it use 64x Zen4c or 32x Zen4? 4-channel or 6-channel ?
I’m not familiar with the Siena platform. If you have a link - I’d appreciate you sharing it. Tia :)
 

TESKATLIPOKA

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May 1, 2020
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I'm more interested in the rumored 'Sarlak' variant with up to 40 RDNA3 CUs.

With something that meaty I could probably just ditch my desktop for all but work related use cases.
You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.

Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.
 
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SteinFG

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Dec 29, 2021
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You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.

Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.
My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.
 

TESKATLIPOKA

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May 1, 2020
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My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.
For that performance, you don't need Sarlak, even Strix point would be enough.
Series S: 20 CUs @ 1.565 GHz, 4.01 TFLOPS
Even Strix with 16CU would need only 2GHz for comparable raw power.
BW would still be a problem, but at least Strix Point wouldn't cost as much as Sarlak.

It's very likely that Strix will be in the next Asus ROG Ally 2 or some different Chinese brand, but 12C24T is a bit of an overkill.
I personally would make an APU: 4xZen5 + 4xZen5c/Zen4c + 20CU + 48MB LCC + 128-bit GDDR5x.
 
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Joe NYC

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Jun 26, 2021
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He does say no to different ISAs or different IPCs. So, again, I’m confident that it’s a no for Zen5 and likely no for Zen6. But, as always, we shall see. All bets are off for AM6.
I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.
 

Joe NYC

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I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).
I seem to recall one version of the rumors that Sienna would have 6 channels of memory.

This, at least, should not be subject to rumors. The Sienna socket is defined, specs are out there, people have answers, but it seems that no one is digging for the answers.

AMD already has enough sockets (not counting legacy) between AM5, SP5 (Genoa), SP6 (Sienna), SH5 (Mi300).

So unlikely that there will be any "enthusiast" level socket. And AMD has always found a way to cripple the Threadripper platform so that it would never be seen as a HEDT platform. We will see if this continues with the next Threadripper on Sienna platform.

The only thing that's left out is the Strix Halo, if it will ever have a socketed version. As I posted above, Strix Halo in AM5 socket, with 4 internal channels and 2 external memory channels would be a very exciting product...
 

Ajay

Lifer
Jan 8, 2001
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I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.

Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.
That sounds like a reasonable interpretation to me.
 

moinmoin

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Jun 1, 2017
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I seem to recall one version of the rumors that Sienna would have 6 channels of memory.
That's not the rumour. SP6/Sienna is 6 ch, SP5/Genoa is 12 ch, those are known. Threadripper so far always has been re-using the server platform, but in case of non-Pro with cut channels. So the rumour went with 8 ch and 4 ch, a cut of a third of the respective server channels.

Anyway as @SteinFG mentioned before AMD already publicly announced unifying both Pro and non-Pro before, so an uncut SP6/Sienna based TR seems most likely at this point.