- Mar 3, 2017
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They'll figure it out eventually. Thermal density is definitely a big problem, especially on newer nodes, but that's the kind of raw engineering problem that engineers love. Maybe they'll flip the stacking or something else, but I doubt V-cache will always come with such a penalty.
Eh, he kinda sidesteps it a little. And the raw technical merit of such a product is very clear. It's not going to happen for the Zen 4 gen, but Zen 5, Zen 6? I think that interview will not age particularly well, and is more targeted in the "selling the products we have today" sense.
???????????????????????????????????????????????????????????????????????????????????????May be something on am6 with zen 6.
I assume Zen 6 will reuse the AM5 socket. But even if they don't, they're not going to move the mainstream off 2ch for cost reasons, nor provision that many extra pins in the socket to support both. Just to steal a pinout from Igor's ARL leak, look how many pins even 2ch takes.???????????????????????????????????????????????????????????????????????????????????????

this is all true and I agree with you with the grand exception of zen 6 being on am5. why i say this? amd is bound to take one big step and mess it all up. by then intel will e on their 2nd new ceo after pat, this ceo being a tuna fish or octopus,I assume Zen 6 will reuse the AM5 socket. But even if they don't, they're not going to move the mainstream off 2ch for cost reasons, nor provision that many extra pins in the socket to support both. Just to steal a pinout from Igor's ARL leak, look how many pins even 2ch takes.
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I think, by what he says, it *won't* be Zen5. Obviously, AMD didn't do it with Zen4 - so he's not talking about that. The point of 'E' cores is Area optimized cores vs performance optimized cores. Personally, I don't see the need for this on the desktop. The current CCD-IOD system offers the flexibility AMD needs for Desktop parts. # of active cores and frequency/voltage/power limits can be set by OEM in the BIOS to get the product that they need for desktop. Mobile is a different story. Servers may be a different story - depending on what customers want (AMD could very easily provide some selective CPUs with a mix of CCDs with performance and high density cores on the same package). I don't see the benefit of having one HP CCD and one HD CCD on the desktop. IMHO.Eh, he kinda sidesteps it a little. And the raw technical merit of such a product is very clear. It's not going to happen for the Zen 4 gen, but Zen 5, Zen 6? I think that interview will not age particularly well, and is more targeted in the "selling the products we have today" sense.
There are 2 ways to interpret it - that hybrid means different instructions sets or different types of cores.Not according to a recent TPU interview with David McAfee
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TPU Interviews AMD Vice President: Ryzen AI, X3D, Zen 4 Future Strategy and More
In this exclusive interview, we talk to the AMD Vice President who's responsible for AMD processors, both on desktop and mobile. Of course we had to ask about AI, but we also learned more about AM5 APUs, core counts, chiplets, Hybrid Architectures, Zen 5 and Intel's x86s proposal.www.techpowerup.com
He does say no to different ISAs or different IPCs. So, again, I’m confident that it’s a no for Zen5 and likely no for Zen6. But, as always, we shall see. All bets are off for AM6.There are 2 ways to interpret it - that hybrid means different instructions sets or different types of cores.
AMD is not going to pair CPUs that differ in the instructions they support. We will see about the other part / other interpretation.
Disclosure: I have you on blocked (so your posts aren't shown unless I am suckered into clicking the show hidden button) because you at one point posted a ton of nonsense, but occasionally something somewhat intelligent wanders from your keyboard to this forum, and I usually find out by others NOT ignoring you..so here we go:Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels
The chances of AMD releasing 4 memory channel socket are near zero.
What could be interesting, if Strix Halo can fit into AM5 socket, would be to have 4 internal memory channels and 2 external.
I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels
The chances of AMD releasing 4 memory channel socket are near zero.
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A 12-core AMD Ryzen 8050 Zen5 "Strix Point" APU has been spotted - VideoCardz.com
The first sign of AMD Ryzen 8050 It is alleged that AMD’s first Strix Point processor has now been spotted over at MilkyWay@Home website. The distributed computing platform, such as MilkyWay@Home, has become a preferred tool for AMD engineers to test unreleased hardware quickly. This approach...videocardz.com
I wonder if it occurred to the VideoCardz guy that the chip might be 12 “Zen 5” cores.
A bit of a ramble:
A lot of people are speculating that AMD will go hybrid on Zen 5, but IIRC Zen 5 work began prior to Intel publicly announcing their efforts. I am not saying this is the case, but I feel like AMD would “play it safe” by introducing a hybrid design with an existing architecture first. I will admit, however that there are some indications that AMD is pursuing a hybrid design for at least some chips.
I guess we will find out in January.
If they go hybrid for desktop, it will be interesting to see if they stick with chiplets since having multiple core designs/configs complicates the design. They would either have to move to 2 CCDs per chiplet or come up with another approach unless they are segregating server from the rest. Any thoughts on this?
I'm more interested in the rumored 'Sarlak' variant with up to 40 RDNA3 CUs.![]()
A 12-core AMD Ryzen 8050 Zen5 "Strix Point" APU has been spotted - VideoCardz.com
The first sign of AMD Ryzen 8050 It is alleged that AMD’s first Strix Point processor has now been spotted over at MilkyWay@Home website. The distributed computing platform, such as MilkyWay@Home, has become a preferred tool for AMD engineers to test unreleased hardware quickly. This approach...videocardz.com
I wonder if it occurred to the VideoCardz guy that the chip might be 12 “Zen 5” cores.
A bit of a ramble:
A lot of people are speculating that AMD will go hybrid on Zen 5, but IIRC Zen 5 work began prior to Intel publicly announcing their efforts. I am not saying this is the case, but I feel like AMD would “play it safe” by introducing a hybrid design with an existing architecture first. I will admit, however that there are some indications that AMD is pursuing a hybrid design for at least some chips.
I guess we will find out in January.
If they go hybrid for desktop, it will be interesting to see if they stick with chiplets since having multiple core designs/configs complicates the design. They would either have to move to 2 CCDs per chiplet or come up with another approach unless they are segregating server from the rest. Any thoughts on this?
Only remaining question is: but what about gaming laptops. Will the 4+8 design be optimal, or will there need to be another pproach instead?
Just want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).
I’m not familiar with the Siena platform. If you have a link - I’d appreciate you sharing it. TiaJust want to say: Threadripper is dropping the difference between pro and non-pro. All future threadrippers will have "pro" features, like high capacity dimm support.
I'm more interested in the cores: if TR on Siena ever comes out, will it use 64x Zen4c or 32x Zen4? 4-channel or 6-channel ?
You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.I'm more interested in the rumored 'Sarlak' variant with up to 40 RDNA3 CUs.
With something that meaty I could probably just ditch my desktop for all but work related use cases.
My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.You don't need Sarlak for that. You can already buy a 16C32T CPU with a much more powerful dGPU, which won't be limited by shared BW or power limit.
40 RDNA3.5 CUs is a lot for an IGP but not for a GPU and thanks to shared power limit you can't expect too high clocks, BW is also pretty questionable.
This Sarlak would be interesting with a competitive price, but I am pretty skeptical about the price.
Sarlak also couldn't be used for PS5 Pro or equivalent Xbox, It just doesn't have a strong enough GPU.
For that performance, you don't need Sarlak, even Strix point would be enough.My dream is microsoft tweaking this chip and making a portable xbox, maybe make it as powerful as Series S. S has 20CUs of RDNA 1.5 running at 100W, I think it's possible to reach this kind of power with sarlak. The problem is the cost obviously.
I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.He does say no to different ISAs or different IPCs. So, again, I’m confident that it’s a no for Zen5 and likely no for Zen6. But, as always, we shall see. All bets are off for AM6.
I seem to recall one version of the rumors that Sienna would have 6 channels of memory.I'd don't know if we ever got updates or rebukes on these rumours since but rumours were that the new Threadripper platforms would be 8 ch (Pro, then likely based on Genoa) and 4 ch (non-Pro, then likely based on Sienna).
That sounds like a reasonable interpretation to me.I think one strong argument in favor of AMD offering a mix with 1 CCD of classic 8 core and another CCD of dense 16 cores is that AMD will have these CCDs already, R+D is done and paid for, no extra resources needed.
Mixing normal and dense cores on the same die - that's probably AMD is going to avoid. It's kind of like spending resources to create an unnecessary complexity.
That's not the rumour. SP6/Sienna is 6 ch, SP5/Genoa is 12 ch, those are known. Threadripper so far always has been re-using the server platform, but in case of non-Pro with cut channels. So the rumour went with 8 ch and 4 ch, a cut of a third of the respective server channels.I seem to recall one version of the rumors that Sienna would have 6 channels of memory.
