Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Page 96 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Abwx

Lifer
Apr 2, 2011
11,557
4,349
136
To just point out the most glaring of many inaccuracies here, 6% better perf/watt means ~6% lower power at iso-frequency, not 15%. Fabs would call the other metric performance. But if I have to once again repeat common knowledge, I think this conversation no longer has value.

That s 6% better perf (not perf/watt) from N4 to N4P wich mean 6% higher frequency at same power, and since TSMC s process scale at P = F^2.6 slope it means that at same frequency power is 1/1.06^2.6, that is 0.86x the power.

From N5 to N4P, since Zen 4 use the former, perf is 11% better at same power, this means that at same frequency power is 1/1.11^2.6 = 0.76x.

The only inaccuracies are from the one that do understand jack to semiconductors physics, i understand better why you thought that Zen 5 wouldnt perform much better...
 
Last edited:

Doug S

Platinum Member
Feb 8, 2020
2,785
4,750
136
That s 6% better perf (not perf/watt) from N4 to N4P wich mean 6% higher frequency at same power, and since TSMC s process scale at P = F^2.6 slope it means that at same frequency power is 1/1.06^2.6, that is 0.86x the power.

From N5 to N4P, since Zen 4 use the former, perf is 11% better at same power, this means that at same frequency power is 1/1.11^2.6 = 0.76x.

The only accuracies are from the one that do understand jack to semiconductors physics, i understand better why you thought that Zen 5 wouldnt perform much better...

Where did you get the information for the exponential function of TSMC's process scaling? Have they actually made that public or are you relying on reverse engineering other data?
 

Abwx

Lifer
Apr 2, 2011
11,557
4,349
136
Where did you get the information for the exponential function of TSMC's process scaling? Have they actually made that public or are you relying on reverse engineering other data?

It can be easily interpolated using frequency/voltage curves of AMD CPUs that you can find here and there, of course this apply not to extreme frequencies where the curve is of cubic shape and even bi-quadratic in the last drops of frequency.

FTR by physical principle a theorical perfect mosfet has a quadratic power/frequency curve, meaning that power increase as a square of frequency, in practice such a perfect behaviour is not achieved, Intel often managed to have a good behaviour with a 2.2-2.3 exponent while TSMC s is closer to 2.6.

But that s not the only parameter at play, TSMC s lower transconductance (wich mean a steeper curve) is compensated by lower capacitance, so at average frequencies their process can have better perf/watt despite slightly higher voltage, the curve is steeper but is translated lower in the power/frequency graph.
 

LightningZ71

Golden Member
Mar 10, 2017
1,798
2,156
136
With AMD essentially stating that they aren't chasing Intel's strategy of shoveling small cores into a processor and, if rumor is to be believed, going so far as to eliminate SMT from at least some future big cores, they will be hard pressed to keep up with MT throughput unless they find a way to realize significant gains in other areas. It seems to me that they will gain significantly in MT performance on the back of two things for Zen5. With the widening of the core, there should be greater opportunities to exploit unused processor resources to enhance SMT throughput. Improving their SMT performance by more than a few percent can certainly make up a lot of ground in MT. In addition, the increased efficiency of N4 in whatever flavor AMD employs it should allow for higher all-core loaded frequencies, or at least effective work done.

If you include that they expect overall IPC for their cores to go up, then their SMT throughput should show a notable rise in general. So, while we believe that Raptor Lake refresh won't see a notable improvement in the E cores, Zen5 should see improvements against their effects.

I don't think that Zen5 suffers against Intel's 15th gen parts in either ST or MT performance.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
With AMD essentially stating that they aren't chasing Intel's strategy of shoveling small cores into a processor
If you look at just AMD's statements on the matter, and ignore the internet commentary, they've said nothing bad about hybrid. Around ADL's launch, they basically just said they would wait till the software ecosystem had adapted. I think it's pretty likely that they will eventually do an 8+16 flagship SKU. The biggest problem is that their small core development is serialized behind the big core, and the desktop chips are the first things they launch on a new arch. They will need to shift to doing those in parallel, but iirc, there were already some rumors along those lines.
 
  • Like
Reactions: Tlh97 and Geddagod

turtile

Senior member
Aug 19, 2014
623
299
136
AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.
 
  • Like
Reactions: Tlh97 and Joe NYC

Thibsie

Senior member
Apr 25, 2017
865
973
136
AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.

That's what I remember too.
They won't do small cores that introduce ISA differences between big and small cores.
Thay might just do as now : see Bergamo or introduce separate small cores but they won't have ISA differences, at least handled (really, not handled at all: just disabled) the way Intel did.
 
  • Like
Reactions: lightmanek

Joe NYC

Platinum Member
Jun 26, 2021
2,539
3,472
106
If you look at just AMD's statements on the matter, and ignore the internet commentary, they've said nothing bad about hybrid. Around ADL's launch, they basically just said they would wait till the software ecosystem had adapted. I think it's pretty likely that they will eventually do an 8+16 flagship SKU. The biggest problem is that their small core development is serialized behind the big core, and the desktop chips are the first things they launch on a new arch. They will need to shift to doing those in parallel, but iirc, there were already some rumors along those lines.
Just FYI, MLID showed some road map where Turin Dense came ahead of regular Turin.

It is not clear how it translates to desktop release schedule, but it seems that the dense CCD is not going to be lagging behind regular CCDs by very long.
 
  • Like
Reactions: Tlh97 and moinmoin

eek2121

Diamond Member
Aug 2, 2005
3,100
4,398
136
AMD didn't say that they won't add small cores. They said that they will not mix cores that need software to run differently on each core. Papermaster also said that the reason they are not going over 16 cores is because the memory can't keep up in a dual-channel format.

I don’t buy that argument about memory bandwidth at all.

Motherboard OEMs are beginning to roll out test BIOS versions with a new AGESA that supports the fastest DDR5 speeds out there. In addition, memory speeds are already significantly faster than what DDR4 is capable of. Intel also has no issues with higher core counts. Finally, who cares if some workloads are limited by bandwidth? The hypothetical 8+16 chip will still be faster.

They could also solve things by moving to a quad channel setup for high end enthusiast offerings.

If they dropped a quad channel board and a 24c CPU that beats up the 7950X many of us would buy it in a heartbeat.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,539
3,472
106
I don’t buy that argument about memory bandwidth at all.

Motherboard OEMs are beginning to roll out test BIOS versions with a new AGESA that supports the fastest DDR5 speeds out there. In addition, memory speeds are already significantly faster than what DDR4 is capable of. Intel also has no issues with higher core counts. Finally, who cares if some workloads are limited by bandwidth? The hypothetical 8+16 chip will still be faster.

They could also solve things by moving to a quad channel setup for high end enthusiast offerings.

If they dropped a quad channel board and a 24c CPU that beats up the 7950X many of us would buy it in a heartbeat.
Considering where things stand:
- AM5 is dual channel
- Sienna platform is (likely) 6 memory channels
- Strix Halo is 4 internal memory channels

The chances of AMD releasing 4 memory channel socket are near zero.

What could be interesting, if Strix Halo can fit into AM5 socket, would be to have 4 internal memory channels and 2 external.
 
Jul 27, 2020
20,040
13,739
146
The chances of AMD releasing 4 memory channel socket are near zero.
Why wouldn't anyone at AMD see an opportunity in that? Enthusiasts already pay quite a bit for the AM5 flagship CPU/mobo combo so they may not mind paying a bit more for a higher end chipset with quad channel RAM. AMD can keep 6,8 and 12 channel RAM for workstation and servers.
 
  • Like
Reactions: Tlh97

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
Why wouldn't anyone at AMD see an opportunity in that? Enthusiasts already pay quite a bit for the AM5 flagship CPU/mobo combo so they may not mind paying a bit more for a higher end chipset with quad channel RAM. AMD can keep 6,8 and 12 channel RAM for workstation and servers.
It would be a large platform investment for a very small volume. Socket and mobo pricing is extremely sensitive to volume. And of course, you'd need a 4ch die...
 

Joe NYC

Platinum Member
Jun 26, 2021
2,539
3,472
106
Why wouldn't anyone at AMD see an opportunity in that? Enthusiasts already pay quite a bit for the AM5 flagship CPU/mobo combo so they may not mind paying a bit more for a higher end chipset with quad channel RAM. AMD can keep 6,8 and 12 channel RAM for workstation and servers.
In their infinite wisdom, AMD marketing determined that "premium" mother board needs 28 USB ports rather than 4 memory channels.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
It is not clear how it translates to desktop release schedule, but it seems that the dense CCD is not going to be lagging behind regular CCDs by very long.
Well if that is the cadence they hold to, it would not be surprising to see an 8+16 SKU as soon as that roadmap aligns. I think that's likely to become AMD's standard high end offering moving forward.
Volume could increase depending on how tangible the gains are.
It's sandwiched between the volumes of mainstream (2ch) client and lower end server (Sienna, 6ch). That's a very narrow product range.

Actually, if there was any desire to go in such a direction, they'd be better off using a physically compatible, but not electrically compatible version of the Sienna socket, just without all the pins used up. That might actually work.

But even if you solve the socket problem, they'd need a new die, which is a big deal. And if memory bandwidth is the only problem, they have other tools available to help, like V-cache and CXL memory expansion with bandwidth aggregation. Realistically, however, I think they'd have no problem doing 8+16 on a 2ch platform.
 
  • Like
Reactions: Tlh97 and Joe NYC

Joe NYC

Platinum Member
Jun 26, 2021
2,539
3,472
106
Well if that is the cadence they hold to, it would not be surprising to see an 8+16 SKU as soon as that roadmap aligns. I think that's likely to become AMD's standard high end offering moving forward.

8 core CCD with V-cache + 16 core CCD without could be a possible top end SKU.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,539
3,472
106
Yeah, I think that's where their vision is heading. Just need to fix most of the clock speed regression with v-cache, and then there really wouldn't be any downside vs 8+8.
It seems AMD needs to overcome the challenges of dissipating the heat from the CPU better. In general CCDs and even more in CCDs with V-Cache.

Short of that, we might see flipping the chips, with big IO die / V-cache on the bottom and compute CCD on top.

RGT mentioned it in one of his videos. Not sure if that came from a real source with knowledge, or reading somebody's (maybe my :) ) posts on Twitter.

BTW, did anyone else noticed that random stuff that RGT guy reads on Twitter, he translates into "people telling him this".
 
  • Like
Reactions: Tlh97 and Exist50

Tuna-Fish

Golden Member
Mar 4, 2011
1,486
2,023
136
In their infinite wisdom, AMD marketing determined that "premium" mother board needs 28 USB ports rather than 4 memory channels.
To be clear, the cost to implement 28 USB ports is minimal compared to the cost of implementing 4 memory channels with DIMMs.

Wider memory interfaces are not common because they are expensive. Especially as the signal path requirements get more stringent with every DRAM generation, making the interface wider also gets proportionally more expensive each generation.

If you want more bandwidth, there is Threadripper. But until expandable/upgradeable main memory goes the way of the dodo, mass market consumer platforms will not get wider. I think Strix halo is AMD's trial balloon here: 256 bit LPDDR5X bus is reasonable in cost to implement, assuming that the DRAM chips are soldered on the same PCB as the CPU. If they are not, it gets expensive. Apple already started doing it, and now AMD is following suit.
 
Last edited:

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
It seems AMD needs to overcome the challenges of dissipating the heat from the CPU better. In general CCDs and even more in CCDs with V-Cache.
They'll figure it out eventually. Thermal density is definitely a big problem, especially on newer nodes, but that's the kind of raw engineering problem that engineers love. Maybe they'll flip the stacking or something else, but I doubt V-cache will always come with such a penalty.
Not according to a recent TPU interview with David McAfee
Eh, he kinda sidesteps it a little. And the raw technical merit of such a product is very clear. It's not going to happen for the Zen 4 gen, but Zen 5, Zen 6? I think that interview will not age particularly well, and is more targeted in the "selling the products we have today" sense.