Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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adroc_thurston

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Intel's big cores after RWC are looking to be really good too.
They're pretty good but I wonder if they're good enough.
20% seems like the floor to me given what AMD accomplished with Zen 3 and what Zen 5 is rumored to be.
Bingo.
It goes way back. People hyped K10 to the moon
Yea it was a rather solid design TLB bugs aside and in itself is a byproduct of like there dead K9 attempts.
Or more recently the claims Zen 2 would be 5GHz.
Only one dumb youtuber did that.
Or bondrewd's misinterpretation of RDNA3.
RDNA3 still works as well as it should in headless compute.
Still a cursed piece of IP.
Sometimes reality does not end up matching unsourced performance projections.
They're not projections, the Si has sampled and perf targets are now final.
 
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soresu

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I've been burnt on so many SRAM/DRAM replacement hopiums that I'd rather not say anything like that ever.

So yea, core bloat is the way forward.
Oh don't get me wrong I've not much hope (especially in DRAMs case - it's a frickin zombie 😂), but if SRAM has run into a scaling wall then the industry has no choice but to take replacements seriously.

That potential replacements like VG SOT MRAM can offer serious area advantages is no small incentive there too.

As long as they could provide adequate power the number of cores per socket could easily increase 50-70% at the same L2/L3 densities in the same space.
 

adroc_thurston

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but if SRAM has run into a scaling wall then the industry has no choice but to take replacements seriously.
Ehhh gonna keep my hopium in "SRAM on CFETs scaling in like early 2030s" instead.
VG SOT MRAM can offer serious area advantages is no small incentive there too.
Yea but SOT-MRAM has so far been a meme, not a product, and I don't think it's anywhere close to being a product.
At least STT-MRAM is real and is slowly replacing eFlash.
As long as they could provide adequate power the number of cores per socket could easily increase 50-70% at the same L2/L3 densities in the same space.
Yea the ideal scenario but that's so unlikely to happen.
 

soresu

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Yea but SOT-MRAM has so far been a meme, not a product, and I don't think it's anywhere close to being a product.
From what I can gather base SOT MRAM doesn't seem worth developing vs the VG SOT variant.

Imec demonstrated VG SOT MRAM in February (link) - they don't seem to do that just for the sake of it given their previous demonstrations of future transistor tech like forksheet.

As you say though it is at the least 5-10 years behind productisation as yet vs STT MRAM which is much more mature.

The advantage of cache stacking though is that AMD at least don't have to wait for a fully CMOS integrated node like STT MRAM has at some fabs.

Another thing being looked at by Imec is nanowire VFETs for SRAM (link), so there's that too I guess.
 

adroc_thurston

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Imec demonstrated VG SOT MRAM in February (link) - they don't seem to do that just for the sake of it given their previous demonstrations of future transistor tech like forksheet.
Yea I've seen the paper, but given thet usual pattern of "imec talks, fabs do not" it's a fair while away from hitting relevant process nodes, unfortunately.
Another thing being looked at by Imec is nanowire VFETs for SRAM (link), so there's that too I guess.
Yea a by far more feasible choice, but either way that's years and years away and we need more SRAM now. Or yesterday, really.
 
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Markfw

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They're pretty good but I wonder if they're good enough.

Bingo.

Yea it was a rather solid design TLB bugs aside and in itself is a byproduct of like there dead K9 attempts.

Only one dumb youtuber did that.

RDNA3 still works as well as it should in headless compute.
Still a cursed piece of IP.

They're not projections, the Si has sampled and perf targets are now final.
I have posted links where Genoa set all sorts of world records, and they say its the fastest. I have posted my own benchmark results and said the same. But there seems to be no love on this forum for Genoa. I hope Zen 5 blows Zen 4 away, but I am more than happy with my 3 Genoa chips.
 

Markfw

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It really does, but 500W socket power bites.

Genoa is still a very-very impressive offering, but per-core/per-thread perf of Turin is something else.
I have all my 7950x chips set to 142-150 watts (depending on BIOS) and my 3 Genoa chips are 320 watt. So I have 608 Zen 4 cores(threads) running at an average of ~4 ghz 100% full load for 1710 watts total. Just the 2 9554's are running a total of 256 threads@3.5 ghz for 640 watts ! 160 more threads @ 4.5 ghz full load. SR/Raptor lake can not touch the performance or the perf/watt. Even at 500 watts, it Zen 5 is that impressive (>20% IPC over Zen 4 + possible clock upgrade), then who cares about 500 watts for 96-128 cores (192=256 threads) for one chip !
 

adroc_thurston

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Even at 500 watts, it Zen 5 is that impressive (>20% IPC over Zen 4 + possible clock upgrade), then who cares about 500 watts for 96-128 cores (192=256 threads) for one chip !
Eh, still tricky to cool, in 1U especially.
>20% IPC over Zen 4 + possible clock upgrade
It's all loaded in IPC, the clocks were effectively tapped out with Zen4 being a real speed daemon.
 

Markfw

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Eh, still tricky to cool, in 1U especially.

It's all loaded in IPC, the clocks were effectively tapped out with Zen4 being a real speed daemon.
Now that could be, but I have seen several WC solutions that would work great, even at 500 watts, but the noise !!!!. Mine are on these:

The 1U and 2U solutions for WC are great, but noisey, and I don't want that, but in a real server floor ? Who cares about the noise.
 
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yuri69

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20% seems like the floor to me given what AMD accomplished with Zen 3 and what Zen 5 is rumored to be.
Lol, what a deja vu from the Zen 4 rumors: "Zen 3 was 20% - now they got the funding, the 5nm doubles everything, the delay between releases gave them such opportunity!!1!"

Thinking like that brought us current Zen 4.

AMD is all about making economical stuff - they will still need to scale it to 4c APUs based on Zen 5. So those uber-wide cores don't really fit.
 

adroc_thurston

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Lol, what a deja vu from the Zen 4 rumors: "Zen 3 was 20% - now they got the funding, the 5nm doubles everything, the delay between releases gave them such opportunity!!1!
Zen4 was always high single digits int, low teens total IPC bump.
AMD is all about making economical stuff
I wouldn't call MI300 economical on a good day.
they will still need to scale it to 4c APUs based on Zen 5
Wroooong because favela/mainstream mobile/edge/Telco segments are served by Compact piles.
 

Mopetar

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Again, it's an Apple-class core.
That's really what you need to know.
Very simple.

I'm taking it to means that it's a much wider design. Depending on how much wider they make it over existing chips and how well they can keep it fed, 20% IPC could be quite conservative.

If logic is the only thing that's scaling well, then logic dictates that there should be an increase in logic. It's only logical after all.
 

adroc_thurston

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I'm taking it to means that it's a much wider design
Yes, that's literally where the entire industry is heading.
Things like Cortex-X4 are just insane in places (10 decode, 10 issue, 8 ALUs, three branch ports, jesus).
If logic is the only thing that's scaling well, then logic dictates that there should be an increase in logic. It's only logical after all.
Bingo, we're entering prime dark silicon spam era for CPUs.
 
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Mopetar

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I don't think we'll see much dark silicon. In the past the newer nodes meant you could cram a lot more in without having to really optimize around space. Wasted space on the newest nodes is almost twice as expensive as the same area on an older node.

Newer nodes having almost the same exponential increase in cost as they offer in transistor density suggests that designs like Zen 4c where the design is made as compact as possible will also become more of a focus.

AMD already seems to have a solution in place to deal with this. Just move more of the cache or the IO to other dies on other nodes where the cost isn't nearly as high. Stacked silicon is going to be more important than ever and I think we're still in the infancy of it.
 

adroc_thurston

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RDOA3 is still too fresh for me to fully trust discord slideware leakers appreciators again.
Happens, my child.
You can still chill N31 at 3.5GHz and enjoy the intended(tm) performance!
Or you can piss off back to /g/, whatever the hell you fancy.
I don't think we'll see much dark silicon.
Zen4 already sees plenty in the FP area so that's inevitable.
like Zen 4c where the design is made as compact as possible will also become more of a focus.
It's just a different core floorplan for a different fmax.
It clocks like Zen1.
Wasted space on the newest nodes is almost twice as expensive as the same area on an older node.
Yea but it's cheap logic, so why not?