Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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moinmoin

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Jun 1, 2017
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Adroc, allow me to move this discussion here. :)
Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.
 

Exist50

Platinum Member
Aug 18, 2016
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Adroc, allow me to move this discussion here. :)

I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.
Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.
 

moinmoin

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Jun 1, 2017
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Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.
Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.
 

Exist50

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Aug 18, 2016
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Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.
I would be surprised if AM5 really had any impact either way. The core design point is unlikely to be dictated by the desktop socket. They will probably take better advantage of the power headroom, but they also probably wanted Zen 5 on N3, so...

I think Zen 5 will be quite a good core. Just not the second coming of Zen. I thought some recently leaks were starting to cool the hype train somewhat.
 
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adroc_thurston

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Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens.
So is Zen5.
but they also probably wanted Zen 5 on N3
Yea, which is like the reason it's as ambitious as it is.
I think Zen 5 will be quite a good core
Literally the best in the entire industry.
Just not the second coming of Zen
It is.
Apple-class cores don't grow on trees.
I thought some recently leaks were starting to cool the hype train somewhat.
What leaks?
 

adroc_thurston

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Wait, so does Zen 5 still use the same Zen 2 style IOD setup with the at this point heavily bottlenecking CCX links?
Yea.
Genoa era c/sIOD's are very very different from Zen2/3 ones anyway.
which reused the IOD of Zen 2 that this carried over to AM5
It absolutely, most definitely did not.
The fabric topology is completely different.
 

DisEnchantment

Golden Member
Mar 3, 2017
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Literally the best in the entire industry
Zen5 is not tiny, not at all.
Do you want to provide background context, quantifiable information even if with caveats/disclaimer, etc. It is quite difficult to have a 'discussion' with only superlative adjectives. Or we can stick to mundane boring discussion without the assertive statements if you don't wish to share stuff. Lots of folks know actual things, but if professional obligations gets in the way we keep our mouth shut and play along ignorant.
It is fine if you don't want to but since the pages are rolling with barely any new information I just want to ask.
 

moinmoin

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Jun 1, 2017
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Eh, twice the speed, half the width.
And it is faster overall.
Zen 3 CCDs have 32B/cycle read/write speed. Zen 4 CCDs have 32B/cycle read and 16B/cycle write speed. Do I fail at reading following slides correctly?

iu

iu
 

adroc_thurston

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Zen 3 CCDs has 32B/cycle read/write speed
It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.
Same rules apply to Genoa/Turin, just that the links themselves clock faster (relatively) and there's more of them.

Oh yea USRs on Navi31/32 are also half the write bandwidth relative to reads.
AMD loves doing this trick to save on active link power it seems.
 

moinmoin

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Jun 1, 2017
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It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.
Same rules apply to Genoa/Turin, just that the links themselves clock faster (relatively) and there's more of them.
So no change. And no change in Zen 5 as well?
Contrast that to Apple's approach where a single core can saturate all of the memory bandwidth. (Not that that would be a good idea with massive multicore chips lol.)
 
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gdansk

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Who doesn't want Zen 5 to be a behemoth? But after all the AMD hype trains who can believe it without evidence. Fool me 7 times shame on me.

They've done well many times but the expectations get out of control. And it is especially hard to believe when they don't really need the rumored performance to beat their competition. 20% IPC seems possibly more than needed.
 

adroc_thurston

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Who doesn't want Zen 5 to be a behemoth?
It literally is.
That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.
But after all the AMD hype trains who can believe it without evidence
like what?
They've been dominating the CPU game (server in particular) for like ~4 years already.
And it is especially hard to believe when they don't really need the rumored performance to beat their competition. 20% IPC seems possibly more than needed.
that's not how you design anything lol
 

moinmoin

Diamond Member
Jun 1, 2017
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AMD hype trains
What are you talking about? adroc just killed my expectation that AMD finally would increase the link speed (per cycle, I know I know) with Zen 5. I'm seriously bummed here, lol.

That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.
Impeccable reasoning.