- Mar 3, 2017
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I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.Adroc, allow me to move this discussion here.
I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.
Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.Nah, on that, at least, he's right. Zen 3 is really its thing. At least from a core perspective.
I would be surprised if AM5 really had any impact either way. The core design point is unlikely to be dictated by the desktop socket. They will probably take better advantage of the power headroom, but they also probably wanted Zen 5 on N3, so...Yeah, the core perspective. That's what it's amounts to which is my point and my expectation for the major difference between Zen 3 and 5, the latter not being limited to just that.
So is Zen5.Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens.
Yea, which is like the reason it's as ambitious as it is.but they also probably wanted Zen 5 on N3
Literally the best in the entire industry.I think Zen 5 will be quite a good core
It is.Just not the second coming of Zen
What leaks?I thought some recently leaks were starting to cool the hype train somewhat.
I forget the specifics, but IPC more in the 20% ballpark. Probably in this thread somewhere.What leaks?
That's just comical.but IPC more in the 20% ballpark
So were Sunny Cove and Golden Cove. Need more than raw size to judge IPC.Zen5 is not tiny, not at all.
Yea but IDC sucks at making good big cores.So were Sunny Cove and Golden Cove
Yea, for that you have a Turin 96c part.Need more than raw size to judge IPC.
Wait, so does Zen 5 still use the same Zen 2 style IOD setup with the at this point heavily bottlenecking CCX links? I thought this was just due Zen 4 being a direct evolution of Zen 3 which reused the IOD of Zen 2 that this carried over to AM5.So is Zen5.
Yea.Wait, so does Zen 5 still use the same Zen 2 style IOD setup with the at this point heavily bottlenecking CCX links?
It absolutely, most definitely did not.which reused the IOD of Zen 2 that this carried over to AM5
The link speed however is still the same.The fabric topology is completely different.
Eh, twice the speed, half the width.The link speed however is still the same.
Literally the best in the entire industry
Do you want to provide background context, quantifiable information even if with caveats/disclaimer, etc. It is quite difficult to have a 'discussion' with only superlative adjectives. Or we can stick to mundane boring discussion without the assertive statements if you don't wish to share stuff. Lots of folks know actual things, but if professional obligations gets in the way we keep our mouth shut and play along ignorant.Zen5 is not tiny, not at all.
Again, it's an Apple-class core.Do you want to provide background context
Zen 3 CCDs have 32B/cycle read/write speed. Zen 4 CCDs have 32B/cycle read and 16B/cycle write speed. Do I fail at reading following slides correctly?Eh, twice the speed, half the width.
And it is faster overall.
It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.Zen 3 CCDs has 32B/cycle read/write speed
So no change. And no change in Zen 5 as well?It was also half the write speed (so 16B), so <8 CCD configs always had reduced DRAM write b/w on Rome/Milan.
Same rules apply to Genoa/Turin, just that the links themselves clock faster (relatively) and there's more of them.
No.And no change in Zen 5 as well?
That's a fabric design choice more or less, not like the core really needs it (see very much-much decent MT scaling on Apple chips).Contrast that to Apple's approach where a single core can saturate all of the memory bandwidth.
It literally is.Who doesn't want Zen 5 to be a behemoth?
like what?But after all the AMD hype trains who can believe it without evidence
that's not how you design anything lolAnd it is especially hard to believe when they don't really need the rumored performance to beat their competition. 20% IPC seems possibly more than needed.
What are you talking about? adroc just killed my expectation that AMD finally would increase the link speed (per cycle, I know I know) with Zen 5. I'm seriously bummed here, lol.AMD hype trains
Impeccable reasoning.That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.
It's literally why Phoenix, LNC and Zen5 look oddly similar.Impeccable reasoning.
Not SRAM, but it won't always be the only player in the game at that latency.Can't spam SRAM, can't scale the frequency anymore so the only choice remains.
I've been burnt on so many SRAM/DRAM replacement hopiums that I'd rather not say anything like that ever.but it won't always be the only player in the game at that latency.
