- Mar 3, 2017
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More ILP is only worth while when the extraction (execution) rate increases - then SMT has less utilization. But, this is heavily implementation dependent and benefits from better tuned machine code. Not saying SMT won’t be used, but there are ways to make it a better choice, rewriting billions of lines of x86 code just isn’t an option. It different in the MacOS/IOS word.Well, this is going to depend a lot on implementation details, but you got that generally backwards. Increased ILP will not scale anywhere near 1:1 as you add more resources to the core. Everything else being equal, when you have more resources sitting idle more often, that is beneficial for SMT.
"Just like other 2016 chips from AMD, “Styx” will be made using 14nm fabrication process at GlobalFoundries."
I think the "roadmap" that quote is referencing ended up being a very well done fake. It had a bunch of stuff like ARM consumer chips. You probably still see some old articles thinking it was real.Was that ever released? Maybe they just felt like reusing the codename.
The only ARM server AMD kinda-sorta released was the Opteron A1100. https://www.anandtech.com/show/8362/amds-big-bet-on-arm-powered-servers-a1100-revealed
Even if the per-thread performance ends up similar, "Thread Director" definitely prioritizes SMT threads last. But in this case, I'm interested in what exactly is making the scheduling decisions. Sounds like they're making this threading info OS visible to assist that side of the scheduling algorithm?
AMD loves reusing codenames.Wait... wut? Codenames are confusing...
bestest way to describe dodge's cars when they first began making durangos. or now im sure.AMD loves reusing codenames.
Durango is whole two AMD parts.
This is interesting. What was canned from the Zen 4 line? We got the same stuff we did for the previous gens plus the "c" core variant, right?Anyway this info is from a old-ish roadmap, about 1/3 of the Zen4/Zen5 products there have been canned, so I wouldn't put too much faith into it being the final codename.
There was supposed to be a Phoenix refresh on 4nm, because originally PHX1 was going to be 5nm.This is interesting. What was canned from the Zen 4 line? We got the same stuff we did for the previous gens plus the "c" core variant, right?
I mean Zen 4 got desktop IOD, server IOD, reusable CCD, an APU, and the additional "c" CCD.
To be fair I'm pretty sure that one is as much a Microsoft part as an AMD one.Durango is whole two AMD parts.
So Bergamo uses the same IOD as Genoa then?I mean Zen 4 got desktop IOD, server IOD, reusable CCD, an APU, and the additional "c" CCD.
Correct.So Bergamo uses the same IOD as Genoa then?
Yea, meet your future overlord.
Maybe not me. I have a 9654 and 2 9554 Genoa..... Waiting to see how much better Zen 5 is.Correct.
Yea, meet your future overlord.
A lot but you pay a power tax.Waiting to see how much better Zen 5 is.
When Mark turns all his computers on, the lights in the neighborhood dimA lot but you pay a power tax.
He should buy a few DGX boxes for a true test of local power grid.When Mark turns all his computers on, the lights in the neighborhood dim
lisa su is a dominatrix?Yea, meet your future overlord.
Games are the workload where HT(SMT) help a lot, If you have a low CPU core count. Of course If you have 8 or more cores It help little.Ok, here goes nothing: the workload where SMT is not very helpful is gaming.
So you can have, say 4 SMT-less, normal-sized cores able to reach 5Ghz running the game's main thread and other high priority stuff for that sweet 120hz goodness, and 8 dense, SMT-capable cores for throughput, running around 3Ghz.
Now, you'll want some more cores for OS background tasks, let's say 4 dense cores for this. You organize this in two 2+6 CCXs which also works well for low-end mobile, and there you go.
The genoa 4 CCD devices don't make too much sense, or at least, it doesn't seem to make that much sense for them to have dual GMI links. They are relatively low clocked parts, but they do have 6 to 8 cores, so it is unclear whether they can actually consume that much bandwidth. If they took an 8 CCD F-series part and connected them with dual GMI links, then that seems to make more sense, although they are lower core count per CCD and higher cache per core.Yep, and it is quite likely that they will, for low core count / high bandwidth needs. They did the same for Genoa already with their 4 CCD SKUs.
You seem to be confusing something:The genoa 4 CCD devices don't make too much sense, or at least, it doesn't seem to make that much sense for them to have dual GMI links. They are relatively low clocked parts, but they do have 6 to 8 cores, so it is unclear whether they can actually consume that much bandwidth. If they took an 8 CCD F-series part and connected them with dual GMI links, then that seems to make more sense, although they are lower core count per CCD and higher cache per core.
If they do have 16 GMI links then why aren't they available now? Are current IO die salvage parts with disabled links? Will there be a new version of the IO die instead? They are a relatively large chip on 6 nm, so having defective parts may be more likely than 14 nm IO die.
your heart is human, your blood is boiling, your brain I.B.M.?Yup it's Styx.
Edited a bit for clarity and readability.You seem to be confusing something:
The current sIOD only has 12 IFoP ports, that is why they can only use narrow mode for the Top end SKUs.
As the IFoP only supplies 64/32 GByte/s/Port, you need wide mode on the low CCD count SKUs in order to be able to make use of those pretty 12 channels of RAM.
And 4 CCD SKU means up to 32 cores, not 6 to 8. To my knowledge, ALL server SKUs <=4 CCD use wide mode - the F-series ones as well.
Locuza already provided an annotated die shot which proved 12 ports - no harvesting.No, I am not confusing anything. The post somewhere above seemed to imply 16 cpu chiplet parts, which would mean they would need 4 ports per quadrant, 16 total. I was refering to 6 to 8 cores per CCD for the 4 CCD devices, but at rather low clock, so it is unclear how much of a difference wide mode will make. The genoa f-series parts are all 8 CCD at 2, 3, 4, or 6 cores per CCD, but if it only has 12 ports, then they cannot be in wide mode. If they use the same IO die for Zen 5, then it may make some sense that the IO die design actually has 16 ports for future use. That is why I was wondering if current IO die parts are salvaged to some extent. Perhaps they are stockpiling fully functional IO die for a future release. It would make some sense for the 6 nm IO die to be more likely to have defects than the old 14 nm IO die. I don't know if they will be using salvage IO die for the SP6 part also, except those may have non-funtional pci-express and memory controllers. I expected a cut down IO die for SP6 given the volume, but who knows.
I wouldn't name Zen 3 along Zen 5. Zen 3 was planned along the first two gens and was (had to be?) built around the existing platform (AM4, IOD) set with the previous gens. I would imagine the designers behind Zen 5 got way more freedom, AM5 was created with Zen 5 in mind and offers plenty headroom Zen 4 isn't exploiting yet, etc. pp. So the possibilities for Zen 3 as a ground up design should easily be dwarfed by Zen 5.Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
