- Mar 3, 2017
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If it will have 16 CCDs, then that seems to imply that the IO die has an extra cpu link that is not currently being used? I wonder if they could build an 8 chiplet device with dual links per chiplet.Zen5 to use CCX design? What's the purpose? Maybe a typo(Zen5c instead of Zen5)?
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Power on usually happens after getting A0 silicon back from the fab doesn't it? If A0 is just out, I'm assuming power on is going to happen at a later date.What, from the tweet, makes you draw this conclusion?
I haven't watched the talk in question, but apparently Papermaster said at the Oracle Exadata server platform launch that Zen 5 samples are running in the lab already.Power on usually happens after getting A0 silicon back from the fab doesn't it? If A0 is just out, I'm assuming power on is going to happen at a later date.
Also for a 1H 2024 launch, I thought they should be on early ES already.
Yep, and it is quite likely that they will, for low core count / high bandwidth needs. They did the same for Genoa already with their 4 CCD SKUs.If it will have 16 CCDs, then that seems to imply that the IO die has an extra cpu link that is not currently being used? I wonder if they could build an 8 chiplet device with dual links per chiplet.


Is this a clue for future SMT4?And thread per cores also, in same register by changing InputEcx.
Engineering samples and early work to verify it for server use I'd imagine.whatever that means
Other way around most likely.Is this a clue for future SMT4?![]()
Man you're gonna give wrong ideas to people like that.Other way around most likely.
4 cores working together to boost a single thread?Other way around most likely.
Lack of SMT in the future.4 cores working together to boost a single thread?
Such a silly idea, but I thought of speculative execution on steroids - instead of guessing the branch and executing it, just split it in 2 and give to 2 cores. then 4, than 8 cores. If a core gets something wrong, flush the whole core 😂4 cores working together to boost a single thread?
Well, nope.Likely SX
AMD always does their own thing that in no way is related to Intel.then that means Zen 5 won't have it either!
I said SX not STX.OK so if Arrow Lake won't have SMT then that means Zen 5 won't have it either!![]()
I like it!Such a silly idea, but I thought of speculative execution on steroids - instead of guessing the branch and executing it, just split it in 2 and give to 2 cores. then 4, than 8 cores. If a core gets something wrong, flush the whole core 😂
Like taking up AVX-512 in consumer space after Intel ditched it?AMD always does their own thing that in no way is related to Intel.
That's the most minor thing imaginable.Like taking up AVX-512 in consumer space after Intel ditched it?
AMD powered refrigerators?Think product segments really.
Yeaaaaaaart gonna stick a new Spartan gen innit.AMD AI powered auto aim handguns?
You not gonna be here in 2 years. It's just a feelingJokes aside, you'll see what I mean in 2yrs give or take.
