Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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jamescox

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Nov 11, 2009
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Geddagod

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Dec 28, 2021
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What, from the tweet, makes you draw this conclusion?
Power on usually happens after getting A0 silicon back from the fab doesn't it? If A0 is just out, I'm assuming power on is going to happen at a later date.
Also for a 1H 2024 launch, I thought they should be on early ES already.
 

uzzi38

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Oct 16, 2019
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Power on usually happens after getting A0 silicon back from the fab doesn't it? If A0 is just out, I'm assuming power on is going to happen at a later date.
Also for a 1H 2024 launch, I thought they should be on early ES already.
I haven't watched the talk in question, but apparently Papermaster said at the Oracle Exadata server platform launch that Zen 5 samples are running in the lab already.
 

BorisTheBlade82

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If it will have 16 CCDs, then that seems to imply that the IO die has an extra cpu link that is not currently being used? I wonder if they could build an 8 chiplet device with dual links per chiplet.
Yep, and it is quite likely that they will, for low core count / high bandwidth needs. They did the same for Genoa already with their 4 CCD SKUs.
 
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DisEnchantment

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Intriguing changes in the Manual few days ago. You can fetch core count per socket from the CPUID ( On Zen 4 only SMU can tell the number of cores a CPU has )
1688502218789.png
And thread per cores also, in same register by changing InputEcx.
1688502281105.png

Usual way was to get thread per core from here
E.4.16 Function 8000_001Eh—Processor Topology Information
Then cores/socket from SMU.