- Mar 3, 2017
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Quantum wells, it's the answer to everything! 🤘how do you plan on cooling this monstrosity Tim?
I'm a bit confused here Doug. IPC is literally, Instructions Per Clock. I used to do calculations on this working on firmware development looking at how long a given instruction took to execute. We had to stick with C/C++ code for portability, but I had no problem tweaking the code to get the compiler to use slightly faster instructions.IPC has plenty to do with clockspeed. IPC will be higher than slower you clock, because DRAM is fewer cycles away. A design that targets a higher clock speed also has to increase cache latency (in terms of clock cycles) at every level; i.e. an L1 able to work at 1 cycle latency at clock x will require 2 cycles latency at clock 2x.
If they increase IPC by 19% it is very unlikely they will be able to maintain the same clock speed. I'm extremely skeptical of any claims that IPC can be increased by that much and clock rates can be increased as well. Sure, they are getting some "free" clock increase due to process, but there's less and less of that available with each process generation.
Even if Zen 5 is a clean sheet, Zen 4 is pretty good. There's no reason to believe we'll have a Zen 1 moment again if for no other reason than we're going to be comparing to something that isn't 15h.Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.
I think people are too locked into the weird geomean amd pushed with the Zen 4 preview last august. the performance leap should be interesting, but the price will be higher than what we've seen. economy should be better then hopefully but who knows.That's a huge jump. It's the same jump that occurred from Zen 2 -> Zen 3.
The words used to describe the new architecture for Zen 5 were the exact same words used to describe the new architecture for zen 3, in both cases AMD said "grounds up".Zen 5's arch is supposed to be the Zen 1 type of clean sheet performance and efficiency overhaul. Why was Mike Clark so excited about it if it's just 19% improved over Zen 4? Why was he so anxious to want to "buy" it? Something doesn't compute.
I expect some interesting things from Zen 5 considering AMD is not developing cores on a shoestring budget anymore since a couple of years now.It's not only about the improvements directly achieved but also the new technologies introduced (which can then be refined) and future improvements enabled by the changes (the usual even Zen gen).
Also the excitement may be not only about the Zen cores but also the package layout with CCDs and one IOD that with Zen 4 was still essentially unchanged since Zen 2.
I'm a bit confused here Doug. IPC is literally, Instructions Per Clock. I used to do calculations on this working on firmware development looking at how long a given instruction took to execute. We had to stick with C/C++ code for portability, but I had no problem tweaking the code to get the compiler to use slightly faster instructions.
What we really have here, and this debate raged on ATF for a while, is Performance Per Clock - which is really an aggregate base on the execution of large instruction stream (from whatever benchmark being used). Ultimately, all I, and I would think most ppl care about is the actual performance delta between a Ryzen 6000 series and an 8000 series APU. +20% is pretty good gen-to-gen nowadays.
I recall this. I remember saying something like this on a now defunct blog but I was toasted in the comment replies. I had the same outlook when Ryzen launched; people presumed AMD were talking out of their ass when they claimed Ryzen would have a giant leap in performance over dozer. I don't remember the exact figure and whether it was overall performance or not. Sure enough they met that goal. Though that being in recent and thus fresh memory has led some of the wild claims about Zen 5 that have been circling like flies to a pile of horse crap. doesn't help when you have morons like mlid talking out of their behinds. Or the chunky boy with greasy curly hair. It's difficult to say what zen 5 would be like or what arrow lake would be like. I can take my best guess and post it here but my words as valid as the bs spewed by leakers.I remember when Apple announced A9 and claimed a 70% performance increase everyone thought that was crazy and they were cherry picking some corner case, then sure enough Geekbench showed a ~70% increase in ST thanks to the combination of IPC improvement along with a massive increase in clock rate. Now maybe they weren't using Geekbench specifically but it was interesting how that lined up so well with their claim in that instance. Obviously Apple was working from a much lower bar back then, everyone is subject to the law of diminishing returns after all.
how do you plan on cooling this monstrosity Tim?
i take back what i said earlier, iw ould love to see 2x 8+16 dies on ryzen. 16 big cores with smt and 32 small cores with cache and smt. cmon amd, make us happy and we'll shower you with our money.
Has anyone here postulated that Zen 5 being on N3 and N4 could mean that the single CCD SKUs may use N4 and the dual CCD ones may use N3? It's also possible that the E-core CCD may use N3 for minimal energy usage while the P-core CCD will benefit from the maturity of the N4 node family?
N4 for APUs and N3 for CCDs?If there is a node split I expect it is more likely to be APUs Vs CCDs.
N4 for APUs and N3 for CCDs?
N4P for everything except Breithorn-Dense.N4 for APUs and N3 for CCDs?
Golden Cove achieved a 19% IPC increase & clocked 0.2GHz higher than Cypress Cove.IPC has plenty to do with clockspeed. IPC will be higher than slower you clock, because DRAM is fewer cycles away. A design that targets a higher clock speed also has to increase cache latency (in terms of clock cycles) at every level; i.e. an L1 able to work at 1 cycle latency at clock x will require 2 cycles latency at clock 2x.
If they increase IPC by 19% it is very unlikely they will be able to maintain the same clock speed. I'm extremely skeptical of any claims that IPC can be increased by that much and clock rates can be increased as well. Sure, they are getting some "free" clock increase due to process, but there's less and less of that available with each process generation.
Frequency iso power. You might be able to hit higher peak ST max, but usually larger architectures take more power to reach the same frequencies as the previous architecture, which is way more of an important limiting factor in MT.Golden Cove achieved a 19% IPC increase & clocked 0.2GHz higher than Cypress Cove.
Zen 3 achieved a 19% IPC increase & clocked 0.2GHz higher than Zen 2.
What is the catch?
Instructions per clock can't be calculated by "looking at how long a given instruction takes to execute", at least not since the days of the 6502 (I remember doing what you are talking about programming an Atari 800's 6502 when I was in junior high) That sort of cycle counting is fine for something like 'MOV R2,0' (assuming you want to deal with figuring out how many instructions can issue and retire in a cycle, which gets more and more complicated the wider CPUs get) but you can't do it for everything.
You can always find the ideal CPI for any instruction just by counting the number of cycles it would take to execute. That may or may not be particularly useful, but I'm not aware of any instruction that takes a variable number of cycles to execute given a perfect cache.
Thankfully I left my assembler programming behind with the 6502 so I couldn't say if current CPUs like Intel/AMD's x86 or Apple/ARM AAarch64 have any instructions with variable timing but I wouldn't be surprised - I'd look at instructions doing stuff like multiplication and division first if I was trying to find such.
Every modern cpu instruction timing is wildly variable. Your 6502 example had memory running zero latency but additional one cycle latency for more than 8 bit addressing. CPU's now have usually 3-level caches for both instruction and data separately, memory is divided to many different timed pages - and usually operate in translated virtual memory meaning that memory access speed in every cache level varies too depending on translation cache hits and misses with page walks -resulting that every instruction execute can vary from one cycle to thousand cycles. And cpu's can reorder instruction to hide that to up to thousand instruction window. So to study how code is executing needs special tools to diagnose it - and for example Intel provides great tools for that.
I think that for Zen 5 generation, AMD will have a native 16 core chiplets, not dual CCD. On N3.Has anyone here postulated that Zen 5 being on N3 and N4 could mean that the single CCD SKUs may use N4 and the dual CCD ones may use N3? It's also possible that the E-core CCD may use N3 for minimal energy usage while the P-core CCD will benefit from the maturity of the N4 node family?
That certainly would be exciting. So Zen 5 is expected to go up to 64 threads?I think that for Zen 5 generation, AMD will have a native 16 core chiplets, not dual CCD. On N3.
That depends. I'd expect for the consumer market, there will always be at least one big 8c CCD with Zen5. The second CCD could be a 16c Zen5c CCD or another 8c - giving you up to 48 hybrid threads.That certainly would be exciting. So Zen 5 is expected to go up to 64 threads?
