AMD should not be stupid enough to make such a config. I't unbalanced CCX configuration which makes thread scheluding absolutely nightmare as for 5 thread job has to choose core per thread from different CCX:s or switch to low-speed CCX.
AMD is stupid enough, never doubt it. They disgraced themselves by releasing abomination Threadripper where half of NUMA nodes had no direct connection to memory, so nothing is too stupid for them. There is no redemption for that, straight to hell.
On topic of two different CCX -> it is as bad as any other hybrid, sharing the same L3 cache domain would not add much, while potentially complicating chip design a lot. AMD loves to do these design as lazy as possible, wasn't some chip in the past with laughable on chip layout, full of space?
For intended aplication it would work just fine, 12C of Zen5 is ton of computing and would marketing people will love Cinebench and stuff scores.