- Mar 3, 2017
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Do you have an AMD press release stating current Turin processors are on N3E? Google AI is saying some of the Turin processors are on N3E (highest end chips) and others are on N4P. That's AI but I always thought all Turin processors would be on at least N3.AMD is using N3E for Turin.
Do you have an AMD press release stating current Turin processors are on N3E? Google AI is saying some of the Turin processors are on N3E (highest end chips) and others are on N4P. That's AI but I always thought all Turin processors would be on at least N3.
There was exactly 1 reference I could get from googling this:Do you have an AMD press release stating current Turin processors are on N3E? Google AI is saying some of the Turin processors are on N3E (highest end chips) and others are on N4P. That's AI but I always thought all Turin processors would be on at least N3.
It's as others have stated. Dense is on n3e and desktop and standard Turin on n4pThere was exactly 1 reference I could get from googling this:
According to AMD, the CCDs on this chip were fabbed on a 3nm process (undoubtedly TSMC’s), with AMD apparently looking to take advantage of the densest process available in order to maximize the number of CPU cores they can place on a single chip.
https://www.anandtech.com/show/2142...-processors-up-to-192-cores-coming-in-h2-2024
There is also Tom's, but not sure how reliable they are:
The Zen 5c models employ up to 12 3nm CCDs with 16 Zen 5c cores per chiplet paired with the same I/O die.
https://www.tomshardware.com/pc-com...gen-zen-5-chips-with-up-to-192-cores-500w-tdp
The CCDs wont be on N3(E?), just the GPUIO die.A lot of companies are using N3E this year, it’s an okay node.
Anyway Zen5 on client isn’t finished yet. Strix halo will be on N3E and will have much better bandwidth.
The CCDs wont be on N3(E?), just the GPUIO die.
