- Mar 3, 2017
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That's probably it for the LPDDR5 devices, yes.This should be the final score. David Huang got exactly 3k for the 5.0GHz SKU at Linux. Linux typically has 5% advantage, so it adds up exactly. Also the newest Lunar Lake result has basically exactly the same per clock performance.
Well then its settled, did not consider Turin for sure, thx for correcting me.Yes, you are completely wrong ;-) and it is precisely because bigger CCDs would not fit under the IHS. And by that I refer to 1 sIOD + up to 16 CCDs having to fit under Turin's IHS. Granite Ridge's IHS would certainly have room for a little bigger CCDs still. (Although maybe Granite Ridge and Turin might receive CCDs at differing steppings, I presume that the design is the same, just like it was shared between desktop and server in Zen1...Zen4.)
BTW, it has been speculated here that the density increase of Granite Ridge's CCD vs. Raphael's is not only thanks to the process bump, but also due to denser L3$ by means of tweaks which are not yet clear.
Apropos, is it just me failing to find the info, or is it true that AMD still haven't said a single word about how Strix Point is divided into core complexes?[...] despite only 24MB L3 cache.
Apropos, is it just me failing to find the info, or is it true that AMD still haven't said a single word about how Strix Point is divided into core complexes?
IIRC I saw a core to core latency graph that showed latency behavior implicating it's a 4 Zen5 CCX and an 8 Zen5c CCX. The latency from the Zen 5 to Zen 5c cores was very high.Sure, but it's not from ---> AMD <--- themselves, is it.
Why did AMD decide to divide the 24MB cache into two slices? Wouldn't there be some penalty by using such design?
It would be because they are two different CCXs most likely... IMO. 4x Zen5 + 16MB, 8x Zen 5c + 8MB.Why did AMD decide to divide the 24MB cache into two slices? Wouldn't there be some penalty by using such design?
So Infinity fabric for inter-CCX communication just like Zen 2?It would be because they are two different CCXs most likely... IMO. 4x Zen5 + 16MB, 8x Zen 5c + 8MB.
Scores are pretty much within margin of error regardless though.The same laptop wouldn't boost to 5.1 consistently with the power plan set to performance earlier.
...and main memory accesses.Infinity fabric for inter-CCX communication just like Zen 2?
Closer to CES 2027 according to rumors.
Regarding CapframeX's not so cryptic tweet. I can believe it. The main reason I believe why is the same IOD & memory limitations of Zen 4. When looking at Zen 4 memory scaling testing for games, 4800 to 6000 shows a real, tangible difference due to the increase being in the same 1:1 ratio. Increases from 6000 1:2 to 8000 1:2 are either very small, or nothing at all. When you look at Intel scaling, they seem to achieve that same boost that AMD gets from 4800 to 6000 all the way to 8000+. No matter how good the core, its going to be limited in this regard. Until AMD improve mem controller and subsystem, the will always be behind the 8 ball in this regard.
CopeChaser for real.Gaming numbers don't seem to be good
It is interesting that Granite Ridges scores noticeably higher than Strix in ST tests per GHz. ~3400pts @ 5.7Ghz ( 596pts/Ghz) Vs ~2900pts @ 5.1Ghz ( 568pts/Ghz) -> that is ~5% IPC difference between two Zen 5 implementations.Scores are pretty much within margin of error regardless though.
Strix got multiple known limitations, namely:It is interesting that Granite Ridges scores noticeably higher than Strix in ST tests per GHz. ~3400pts @ 5.7Ghz ( 596pts/Ghz) Vs ~2900pts @ 5.1Ghz ( 568pts/Ghz) -> that is ~5% IPC difference between two Zen 5 implementations.
AMD haven't publicly said anything about Strix Point's microarchitecture differing¹ from Granite Ridge's/ Turin's, have they? ... To be fair, we are still pre-launch, so it's somewhat natural that they aren't particularly talkative about details like that for the time being.half (or less?) AVX512 throughput
AMD public statements are driven by marketing... David Huang benched Strix Point and found the AVX512 throughput being the same as Zen 4 and, at the same time, both CCXes being architecturally identical.AMD haven't publicly said anything about Strix Point's microarchitecture differing¹ from Granite Ridge's/ Turin's, have they? ... To be fair, we are still pre-launch, so it's somewhat natural that they aren't particularly talkative about details like that for the time being.
¹) WRT FP pipelines, if true. I thought that'll only happen to Strix Halo's low power cores.
Well to be fair, he said he tested a pre-prod. laptop with ES CPU. Still, Strix Point seems to have power optimized Zen 5 core.AMD public statements are driven by marketing... David Huang benched Strix Point and found the AVX512 throughput being the same as Zen 4 and, at the same time, both CCXes being architecturally identical.
Noted, thanks. Fixed original comment.@techjunkie123, review the CPU forum rules please.
That was from David Huang, with the 4+6 SKU:IIRC I saw a core to core latency graph that showed latency behavior implicating it's a 4 Zen5 CCX and an 8 Zen5c CCX. The latency from the Zen 5 to Zen 5c cores was very high.

