Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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eek2121

Diamond Member
Aug 2, 2005
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How did you manage to bring Intel's outdated turbo tables into a Zen thread? The only frequency hardcoded in today's Zen chips should be the upper limit, everything else depends on cooling headroom.
AMD does indeed put limits into their silicon (and AGESA). This was discussed elsewhere and I believe AMD also mentioned this during a video once. FMAX is only one of those limits.

Those limits are disabled when overclocking, of course.
 

Exist50

Platinum Member
Aug 18, 2016
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But I'm getting the impression AMD likes to call the inclusion of the AI Engine hybrid as well.
That's more under the umbrella of what they used to call "Fusion". I think if AMD talks about hybrid in marketing, they will either use the term for the mix of CPU cores, or just invent a new term altogether. Well, that would at least be the sane way to brand things. We'll see what their marketing department thinks...
 

moinmoin

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Jun 1, 2017
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That's more under the umbrella of what they used to call "Fusion". I think if AMD talks about hybrid in marketing, they will either use the term for the mix of CPU cores, or just invent a new term altogether. Well, that would at least be the sane way to brand things. We'll see what their marketing department thinks...
No, Fusion is from a decade ago. I was thinking of Papermaster's interview from May:

"Paul Alcorn: So, it's probably safe to say that a hybrid architecture will be coming to client [consumer PCs]?

Mark Papermaster: Absolutely. It's already there today, and you'll see more coming.
"


There is no big.LITTLE alike product on the market by AMD right now. (Big) Phoenix with its AI Engine however is already available. While Little Phoenix with its supposed mix of cores is MIA (and people like Ian Cutress talk like it doesn't exist/isn't mixing cores). Or what do you think Papermaster is referring to?
 

jpiniero

Lifer
Oct 1, 2010
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There is no big.LITTLE alike product on the market by AMD right now. (Big) Phoenix with its AI Engine however is already available. While Little Phoenix with its supposed mix of cores is MIA (and people like Ian Cutress talk like it doesn't exist/isn't mixing cores). Or what do you think Papermaster is referring to?

Little Phoenix is probably what he's talking about.
 

Exist50

Platinum Member
Aug 18, 2016
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No, Fusion is from a decade ago. I was thinking of Papermaster's interview from May:

"Paul Alcorn: So, it's probably safe to say that a hybrid architecture will be coming to client [consumer PCs]?

Mark Papermaster: Absolutely. It's already there today, and you'll see more coming.
"


There is no big.LITTLE alike product on the market by AMD right now. (Big) Phoenix with its AI Engine however is already available. While Little Phoenix with its supposed mix of cores is MIA (and people like Ian Cutress talk like it doesn't exist/isn't mixing cores). Or what do you think Papermaster is referring to?
I think it's useful to include the context:
But what you'll also see is more variations of the cores themselves, you'll see high-performance cores mixed with power-efficient cores mixed with acceleration. So where, Paul, we're moving to now is not just variations in core density, but variations in the type of core, and how you configure the cores. It's not only how you've optimized for either performance or energy efficiency, but stacked cache for applications that can take advantage of it, and accelerators that you put around it.

When you go to the data center, you're also going to see a variation. Certain workloads move more slowly [...] You might be in that sweet spot of 16 to 32 cores on a server. But many businesses are indeed adding point AI applications and analytics. As AI moves from not only being in the cloud, where the heavy training and large language model inferencing will continue, but you're going to see AI applications in the edge. And it's going to be in enterprise data centers as well. They're also going to need different core counts and accelerators.
Paul Alcorn: So, it's probably safe to say that a hybrid architecture will be coming to client [consumer PCs]?

Mark Papermaster: Absolutely. It's already there today, and you'll see more coming.
So it's tough to say what he means in particular, but he is lumping in V-cache SKUs under the "hybrid" umbrella, so maybe that's the intended reference?

All just semantics at the end of the day, but I hope they don't overload existing terms too much, at least in anything public-facing.
 
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dr1337

Senior member
May 25, 2020
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That is certainly not what Raptor Lake benchmarks show.
1920-1080.png
9 games having a significant preference for E cores disabled certainly isn't nothing. And with at least 25 games being basically equal, within a realistic margin of error, it would seem E cores are seriously under-utilized in gaming. Makes me wonder now how this chart would look if both configurations were at maximum OC. Surely turning off 16 extra cores would net more headroom for the P cores to clock a bit higher.
 

Exist50

Platinum Member
Aug 18, 2016
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9 games having a significant preference for E cores disabled certainly isn't nothing
But the average is 1%, and at 1080p with a 4090. Higher resolution and ray tracing would all be likely to flip that gap. Either way, I don't think that's a meaningful difference. Plus, most of the penalty is likely to be the still extant (albeit smaller) hit to ring clock speeds, which AMD would not have a problem with in a two CCD hybrid approach.
it would seem E cores are seriously under-utilized in gaming
Well yeah, games in general make terrible use of modern high end chips. That's what I was saying earlier about the second CCD for the 7950x being useless for gaming. If you have the game pinned to one CCD, as it typical right now, whatever you do to the other is unlikely to matter. That's why I think it's much more sensible to talk about the productivity benefit of a hybrid setup.
Surely turning off 16 extra cores would net more headroom for the P cores to clock a bit higher.
For both Intel and AMD, gaming workloads simply do not push the processors' power limits. For example, ComputerBase measured 141W for the 13900k, 105W for the 7950X, and 72W for the 7950X3D. All well below their respective boost power limits. Thermal density (cooling) and silicon limitations are more likely to limit gaming performance than power.

Also, that's a problem better suited for the scheduler to solve. If some threads can run more efficiently on dense cores, that will better free up headroom than disabling them.
 

eek2121

Diamond Member
Aug 2, 2005
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Here is your answer for hybrid:


If this is true, looks like it is launching on the mid-low end.

AMD managed to get the die size down to 137mm2. I am curious as to how they are doing this. Multi-die or mixing HP/HD libs on one die? Hopefully we get details soon.

Side Note: Would love to see them add (“small”) cores to the IO die for Zen 5. That would be one way to add cores without having to make multiple types of chiplets.
 

deasd

Senior member
Dec 31, 2013
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Here is your answer for hybrid:


If this is true, looks like it is launching on the mid-low end.

AMD managed to get the die size down to 137mm2. I am curious as to how they are doing this. Multi-die or mixing HP/HD libs on one die? Hopefully we get details soon.

Side Note: Would love to see them add (“small”) cores to the IO die for Zen 5. That would be one way to add cores without having to make multiple types of chiplets.
There are 6 Zen4 cores being shrinked to 4 Zen4C while use 4CUs GPU instead of 12CUs, only result in ~23% smaller die size??? If true what's the point of this design? I think even 6 OG Zen4 and 4CUs can do 137mm2. Something is not right.....(But this is Zen5 thread, so....)
 
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Abwx

Lifer
Apr 2, 2011
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Here is your answer for hybrid:


If this is true, looks like it is launching on the mid-low end.

AMD managed to get the die size down to 137mm2. I am curious as to how they are doing this. Multi-die or mixing HP/HD libs on one die? Hopefully we get details soon.

Side Note: Would love to see them add (“small”) cores to the IO die for Zen 5. That would be one way to add cores without having to make multiple types of chiplets.

All this doesnt make much sense on a cost perspective, if they do a 2 Zen 4 + 4 Zen 4c then they cant harvest efficently chips that have a non functional Zen 4 core and would be left with 4 Zen 4c cores, and if one Zen 4c is non functional that would get them a 2 + 2.

If that s 4 Zen 4 + 2 Zen 4c instead then a faulty Zen 4 core would lead to a 2 + 2, while a faulty Zen 4c would yield a 4 + 0.

Most logical would be to use 6 regular Zen 4 cores to get rid of those complicated and innefficient arrangements, the fact that the die is only 23% smaller despite a drastically cut down GPU and no AI is a hint that there s no c cores here.
 

Tuna-Fish

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Mar 4, 2011
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All this doesnt make much sense on a cost perspective, if they do a 2 Zen 4 + 4 Zen 4c then they cant harvest efficently chips that have a non functional Zen 4 core and would be left with 4 Zen 4c cores, and if one Zen 4c is non functional that would get them a 2 + 2.

If that s 4 Zen 4 + 2 Zen 4c instead then a faulty Zen 4 core would lead to a 2 + 2, while a faulty Zen 4c would yield a 4 + 0.

Most logical would be to use 6 regular Zen 4 cores to get rid of those complicated and innefficient arrangements, the fact that the die is only 23% smaller despite a drastically cut down GPU and no AI is a hint that there s no c cores here.

They can harvest everything for the very low-end embedded stuff they sell. Things like POS terminals and machines that display ad screens are something AMD still sells a bunch of, even if the margins are so low it's barely visible in their bottom line. Anything that has a display out and at least one working x86 core has a place where it can be sold, even if the prices are not very interesting for AMD.
 

Abwx

Lifer
Apr 2, 2011
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They can harvest everything for the very low-end embedded stuff they sell. Things like POS terminals and machines that display ad screens are something AMD still sells a bunch of, even if the margins are so low it's barely visible in their bottom line. Anything that has a display out and at least one working x86 core has a place where it can be sold, even if the prices are not very interesting for AMD.

That s a possibility but using regular Zen cores on 4 cores would require only 8mm2 more or so, that s a negligible saving to cram 4 Zen 4c cores for a much lowered ASP, by using the same cores as Phoenix they are also savingthe cost to shrink Zen 4c to 4nm since they were designed for a 5nm process, that s quite a hassle for not much.
 

SteinFG

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Dec 29, 2021
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There are 6 Zen4 cores being shrinked to 4 Zen4C while use 4CUs GPU instead of 12CUs, only result in ~23% smaller die size??? If true what's the point of this design? I think even 6 OG Zen4 and 4CUs can do 137mm2. Something is not right.....(But this is Zen5 thread, so....)

Small phoenix has same L3 cache (16MB), same Media engine, Same USB/Sata controllers, Same 128bit DDR5 memory PHY, Same Display controllers. That's why it hasn't shrunk a lot.

It's hard to shave off silicon area. You have to sacrifice a lot to get an even smaller die size. For example, "Zen 2" Renoir is 158mm², and to get to 100mm² (mendocino), they've cut out: 20 out of 24 pcie lanes, leaving only 4 in there; 6 out of 8 compute units, leaving only 2 CUs; bunch of usb; all sata; half the memory bus; half the cores; half the cache.

Zen 4c is in there for lower power use, mostly.
 
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Abwx

Lifer
Apr 2, 2011
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Small phoenix has same L3 cache (16MB), same Media engine, Same USB/Sata controllers, Same 128bit DDR5 memory PHY, Same Display controllers. That's why it hasn't shrunk a lot.

It's hard to shave off silicon area. You have to sacrifice a lot to get an even smaller die size. For example, "Zen 2" Renoir is 158mm², and to get to 100mm² (mendocino), they've cut out: 20 out of 24 pcie lanes; 6 out of 8 compute units; bunch of usb; all sata; half the memory bus; half the cores; half the cache.

Zen 4c is in there for lower power use, mostly.

From 6 to 8CUs is by far not as much as 12 to 4 CUs, and yet Mendocino was die reduced by a 1.5 factor while PHX to PHX2 is only reduced by 1.3 factor, granted the core count is reduced by only 1.33x but cores are tiny compared to the GPU part wich should be allocated about 40-50% in PHX.
 

SteinFG

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Dec 29, 2021
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From 6 to 8CUs is by far not as much as 12 to 4 CUs, and yet Mendocino was die reduced by a 1.5 factor while PHX to PHX2 is only reduced by 1.3 factor, granted the core count is reduced by only 1.33x but cores are tiny compared to the GPU part wich should be allocated about 40-50% in PHX.
I think you missed: They've cut out 6 out of 8, leaving only 2. And they've cut out L2 iGPU cache in mendocino too. I've edited my comment to make it more obvious
 

aigomorla

CPU, Cases&Cooling Mod PC Gaming Mod Elite Member
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Regarding your comments about @Markfw , uncalled for. IMO. Many of us are pretty neutral about who makes our hardware, as long as it performs great. Intel is significantly trailing AMD in perf/watt and so many of us won’t use them because of that.

So what @Markfw said was false, and was exactly what I disagreed with.


BOTH of you guys will be put on NOTICE.
The Forum will not be split up because of two people and their views.
You will NOT call out other members, and you will follow rules.

I WILL NOT repeat myself again, if I see another call out in any kind, i will imediately give you a infraction so fast, not even the Road Runner will have enough time to say his iconic "BEEP BEEP", before you are Ding'd.

Keep on topic, and DO NOT call out members.
There are better ways to disagree and debate without pointing out members or calling people out.

Moderator Aigo
 
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burninatortech4

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Jan 29, 2014
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Here is your answer for hybrid:


If this is true, looks like it is launching on the mid-low end.

AMD managed to get the die size down to 137mm2. I am curious as to how they are doing this. Multi-die or mixing HP/HD libs on one die? Hopefully we get details soon.

Side Note: Would love to see them add (“small”) cores to the IO die for Zen 5. That would be one way to add cores without having to make multiple types of chiplets.
What about the possibility of "shadow" cores that aren't OS transparent but are present on the I/O die? I think Meteor Lake has 2 low power cores on the SOC die that aren't OS transparent?
 

Exist50

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Aug 18, 2016
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What about the possibility of "shadow" cores that aren't OS transparent but are present on the I/O die? I think Meteor Lake has 2 low power cores on the SOC die that aren't OS transparent?
I don't think "OS transparent" cores are a thing. At least not when talking about application processors. Applies the same for AMD and Intel.
 

Abwx

Lifer
Apr 2, 2011
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I think you missed: They've cut out 6 out of 8, leaving only 2. And they've cut out L2 iGPU cache in mendocino too. I've edited my comment to make it more obvious
Well see when there s something actually released, FTR the 6C/4C clock at 4.9/4.7GHz respectively, that s quite high frequencies typical of a regular Zen 4 since they are also 28W TDP limited, quite unlikely that for the 4C version they would go as far as using a single Zen 4 core and 3 Zen 4c cores if they are to recycle partly faulty parts.
 

A///

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Feb 24, 2017
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I don't think "OS transparent" cores are a thing. At least not when talking about application processors. Applies the same for AMD and Intel.
Doesn't matter does it? People complain about Intel's Thread Director and how the IOD handles cores on AMD but the real problem here is Microsoft and how their thread handling works// regardless of how much damn handholding microsoft is given by these two companies m$ still walks into a wall, consistently and without fail.

is it no wonder that intel's big little or amd's monster core systems work better by large gaps on linux? maybe some software person can chime in and explain why other than the long and ragged reasoning that windows carries a lot of legacy code whoopie doo.
 

burninatortech4

Senior member
Jan 29, 2014
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Sorry, maybe I'm using the wrong terminology. I just mean cores present on the I/O die that Windows can't access directly but are present for background tasks (I can't define that right now). I'm pretty sure there was discussion about cores on the Intel Meteor lake SOC die. What are the chances AMD does something like that?