Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Joe NYC]

The fact that Zen 5 has a separate V-cache variant (according to AMD roadmaps) makes me think that V-cache still will not be standard for zen 5.

Hmm... Good point, I forgot about that. Mike Clark discussed that, in interview with Ian, that there is flexibility in not making V-Cache mandatory...

I wonder if market situation changes this. It looks like there will be a glut of fab capacity, while there was shortage during that interview.

TSMC will have a desire to sell all its wafers. With V-Cache, AMD can take up a bunch of N6 capacity, employ TSMC packaging to full capacity and turn incremental $10 cost (AMD would pay TSMC) into $50 MSRP increase that customers would gladly pay.

It would seem like a good recipe for the lean times ahead...

 

[Panino Manino]

And yet, the performance jump is the biggest since the jump from construction cores to Zen 1.

What a complete failure, correct?

I didn't imply that (but personally I was expecting it to come a bit more ahead of AD).
But this makes the "Christ is returning hype" even worse. If Zen 4 improved so much with so little effort than the Earth will Stood Still to witness Zen 5 launch.

Maybe this is a consequence of Zen 1 real performance.
I remember people expecting much less before launch but it surpassed everyone's expectations a bit. Except Zen+ every generation got better and this got people used to expect the most ludicrous rumors (just think how much people still give time and attention to "that" youtube channel).


The good times are over, now AMD still alone anymore, Intel is back into competition.

 

[tomatosummit]

I didn't imply that (but personally I was expecting it to come a bit more ahead of AD).
But this makes the "Christ is returning hype" even worse. If Zen 4 improved so much with so little effort than the Earth will Stood Still to witness Zen 5 launch.

Maybe this is a consequence of Zen 1 real performance.
I remember people expecting much less before launch but it surpassed everyone's expectations a bit. Except Zen+ every generation got better and this got people used to expect the most ludicrous rumors (just think how much people still give time and attention to "that" youtube channel).


The good times are over, now AMD still alone anymore, Intel is back into competition.

The hype has been pretty absurd recently. Everytime an employee gets an interview they will say "next product is great, going to better than last one", no ship, they're not going to claim it's worse in any capacity.
And we've had years of huge performance upgrade claims from intel while what we got was fairly tepid even with claims of totally new core designs, or how zen3 was the greatest thing in the world but was generally 10% faster in MT, the hype has wierd targets and the counter-hype machines really don't help either.

I feel like after a decade of bulldozer and 2500k eternal that's ended with zen4 and golden cove we've caught up to where we should be and performance increases will slow down a bit, overclocking zen4 well beyond it's efficient point is another telling symptom. Going back to more cores thankfully.

Which is why I want to be quite conservative with my own zen5 expectations. Like the core will be a little better and I'll buy the rumous of double core counts but it's more of how that's achieved.
If it's just more cores on a ccd then perhaps they can push the core design further without much risk.
Or it's a new ccx stacked on some interposer with off chiplet cache layouts being changed. I could see that as eeking out more efficiency in various places but not neccesarrily being a per core performance increase, at least for the high performance desktop.

 

[Geddagod]

Results is all I care about, and it delivers. Why would you care how it is designed if it works so well ????

Because that's not what we were talking about???
Zen 4 wasn't the grounds up design like the rumors were talking about. Overblown hype train rumors of 40 percent IPC was exactly that- hype.

 

[Geddagod]

I think expecting some massive architectural rework never made sense for the follow-up to Zen 3, although I was still disappointed by Zen 4, partially due to the more optimistic rumors. I tempered my expectations as we got closer to the reveal, and I was still let down. Rumors of Zen 5 being huge and the largest change to the core, among other things, since Zen, have been around for a long time and I always expected it to be more than whatever Zen 4 ended up being (which is, admittedly, not much). I'm not the only one, either. The interviews with Mike Clark and such make me pretty hopeful.

Anyway, I hope that AMD picks up the pace and we get no more Zen 4s in the near future. It's certainly in their interest, because they could get lapped by Intel in 2025 and later if most of their ambitious plans on both the process and CPU design side are realized and Royal Cove is even half as good as some of the rumors say.

Ye it didn't really make sense for zen 4 to be a huge architectural rework when literarily the prior generation was claimed to be a grounds up design. But hindsight is 20/20

 

[Markfw]

Because that's not what we were talking about???
Zen 4 wasn't the grounds up design like the rumors were talking about. Overblown hype train rumors of 40 percent IPC was exactly that- hype.

So you are going to blame AMD for rumors ??? Get a life,.

 

[Geddagod]

I think we won't get another Zen 4-esque architecture unless a few things happen:
1) AMD's financial situation does not allow them to put enough engineering resources to perform a grounds-up redesign.
2) A completely new DT platform/socket is being designed such that it pulls engineering resources away from the core design.

I think the current Zen 4 launch is a consequence of the above conditions considering that Zen 4 was likely designed in 2018, which is before they were financially on solid ground, and it coincided with them needing to design a new socket/platform from scratch. Zen 1+, Zen 2 and Zen 3 had the luxury of the AM4 socket already existing so they could focus more effort on the core and core package design. As a platform, AM5 should not have the same weaknesses and shortcomings of AM4 from a longevity standpoint. It should have enough on-board BIOS memory to accommodate all future AM5 processors without needing to worry about compatibility or BIOS updates, and the socket power is beefed up to handle future 24 core processors, should they exist. PCIe Gen 5 is supported out of the gate (at a cost premium) but the future proofing is there if you want it. It would not surprise me if all of this effort meant that AMD did not have enough resources to do a grounds-up redesign for Zen 4. Yes, we probably were all expecting some kind of crazy uplift given the new N5 node, but it was likely more economical to just make Zen 4 basically a die shrunk Zen 3 with your run-of the-mill enlarged structures, extra transistors to enable the higher clocks, and QOL improvements, e.g. VNNI and AVX-512.

I don't think it has to do with their financial standpoint as much as making sure they don't put too much on their plate like Intel did and then fail to deliver. Intel used to have a bunch of resources too, but they went way too ambitious and then failed to deliver. Doing a new grounds up design every generation just doesn't make a lot of sense imo. This is compounded by the fact that zen 3 was a grounds up design, so I'm willing to bet their was at least SOME low hanging fruit from the zen 3 design they can tweak to get gains.
Zen 4 did improve a lot of stuff, and overall perf gain was still very large, so AMD might have thought they didn't *need* a architectural redesign regardless. I doubt it's because of financial stuff like not being able to afford to redesign or not having enough resources too.

 

[Geddagod]

So you are going to blame AMD for rumors ??? Get a life,.

When? What??

 

[DrMrLordX]

When? What??

Um

Zen 4 wasn't the grounds up design like the rumors were talking about.

That?

 

[Geddagod]

Um



That?

How exactly is that me blaming AMD for rumors, rather than just saying the rumors were wrong?

 

[Exist50]

Um



That?

Wait, how is pointing out that the rumors were wildly overhyped and off base equivalent to blaming AMD? If anything, you're implying that AMD is the source...

 

[DrMrLordX]

How exactly is that me blaming AMD for rumors, rather than just saying the rumors were wrong?

Because

You're kidding. Zen 4 rumors peaked at huge 20-40 percent IPC gains! Many people thought that zen 4 was going to be a huge architectural uplift.

AMD has clearly stated that Zen5 will be a major rework. Here you are responding to a forum member echoing those statements from AMD. You're effectively saying "AMD is wrong to say this about Zen5 because look how the Zen4 rumours turned out?!?!?!" which blames AMD for Zen4 rumours. Not hard to figure it out yo.

 

[Exist50]

I didn't imply that (but personally I was expecting it to come a bit more ahead of AD).
But this makes the "Christ is returning hype" even worse. If Zen 4 improved so much with so little effort than the Earth will Stood Still to witness Zen 5 launch.

Maybe this is a consequence of Zen 1 real performance.
I remember people expecting much less before launch but it surpassed everyone's expectations a bit. Except Zen+ every generation got better and this got people used to expect the most ludicrous rumors (just think how much people still give time and attention to "that" youtube channel).


The good times are over, now AMD still alone anymore, Intel is back into competition.

I think there's a certain irony in all this coming fresh off of a generation that defied the rumors in every possible way. And yet, despite being one of AMD's smaller gen/gen architectural jumps, it provided some of the greatest gains in performance and efficiency, driven by process and good physical design work. Perhaps an indication that we're focusing on the wrong indicators.

AMD has clearly stated that Zen5 will be a major rework. Here you are responding to a forum member echoing those statements from AMD.

We have absolutely no idea what "major rework" translates to. Intel Sunny Cove was a "major rework", and we all saw how that ended up. Hell, Bulldozer was! The term means nothing by itself. And Zen 4 showed that the rumor mill (or at least certain purveyors...) are absolutely worthless, so we're left to guess and assume.

Now, putting aside the examples I simply listed for illustration's sake, one reasonable guess would be that Zen 5, as a supposedly larger architectural change, will bring a greater gen/gen IPC improvement than Zen 4. Ok, so let's say >13% IPC as our baseline, with unknown impact to frequency and power @ iso-process. Then we have N5P->N4P, which is supposed to give something like +4% perf @ iso-power.

Anything beyond this is basically the realm of pure speculation, as far as I see it. We can make reasonable guesses. For example, we could assume that AMD doesn't want frequency to regress vs Zen 4. We could even say they want to use all of the process improvement towards hitting 6GHz (so about the same critical path length as Zen 4). All perfectly reasonable, but guesses nonetheless. You could pick any number you want for IPC. 20%, 30%, even 40%. Some might be more reasonable than others, but all are just guesses. But that's the thing. These are guesses from random people on the internet, not statements from AMD. So why respond so vehemently to someone pointing out how the last round of guessing ended?

 

[Geddagod]

Because



AMD has clearly stated that Zen5 will be a major rework. Here you are responding to a forum member echoing those statements from AMD. You're effectively saying "AMD is wrong to say this about Zen5 because look how the Zen4 rumours turned out?!?!?!" which blames AMD for Zen4 rumours. Not hard to figure it out yo.

No I'm not. What you are doing is putting words in my mouth. I literarily said before, in this forum, that I expect Zen 5 to be a 'golden cove' or 'zen 3 moment' for AMD, or bigger. Because AMD called zen 3 an architectural rework as well.
I was replying to people talking about how recent products have been getting overhyped. I agreed with him. I don't believe in the 40% IPC rumors of zen 5, because of said hype train. That has NOTHING to do with me blaming AMD, because AMD didn't even MAKE a claim about Zen 5 performance!

 

[Exist50]

Hmm... Good point, I forgot about that. Mike Clark discussed that, in interview with Ian, that there is flexibility in not making V-Cache mandatory...

I wonder if market situation changes this. It looks like there will be a glut of fab capacity, while there was shortage during that interview.

TSMC will have a desire to sell all its wafers. With V-Cache, AMD can take up a bunch of N6 capacity, employ TSMC packaging to full capacity and turn incremental $10 cost (AMD would pay TSMC) into $50 MSRP increase that customers would gladly pay.

It would seem like a good recipe for the lean times ahead...

I think the big question is simply the manufacturing volume of hybrid bonding. It will take a lot of extra equipment to scale from a few niche product lines to basically everything they sell. Would make sense for that to take a few years.

But I think somewhere in the N3 generation it would make sense for them to go all-in. N3 SRAM scaling is horrible, and yet you pay the N3 premium anyway. That might be the economic incentive AMD needs.

 

[moinmoin]

I'd personally hope people stop complaining about hype in a Zen 5 hype thread. I want more tech discussion, what little tech nuggets we get are always drowned anyway.

We have absolutely no idea what "major rework" translates to.

There are patterns AMD followed so far. With Zen 1 and 3 "ground up design" translated to a restructured core where some IP blocks can be relocated from earlier designs but the whole arrangement is all new. Zen 2 and 4 were extensions, the structure is the same, "only" within the IP blocks there were changes done.

The comparison with Intel is hard as they appear to apply only the latter approach.

 

[DisEnchantment]

I want more tech discussion

No you cannot. You should stay in rear view mirror.

 

[DrMrLordX]

No I'm not. What you are doing is putting words in my mouth.

Okey dokey. I'll try not to quote you anymore then. Seems you don't appreciate it.

 

[Doug S]

I think the big question is simply the manufacturing volume of hybrid bonding. It will take a lot of extra equipment to scale from a few niche product lines to basically everything they sell. Would make sense for that to take a few years.

But I think somewhere in the N3 generation it would make sense for them to go all-in. N3 SRAM scaling is horrible, and yet you pay the N3 premium anyway. That might be the economic incentive AMD needs.

The issues with SRAM scaling will be alleviated somewhat with GAA and BPR coming in the N2 generation, though it remains to be seen to what extent. There are also other options like Zeno bit cells or eDRAM (which IBM has already been using for years) for higher capacity last level caches.

So I'm not sure it would be worth putting in place the level of infrastructure required to pursue a 'hybrid bonding for all' strategy for a single node. Plus for most buyers of laptop/desktop CPUs they are already more than fast enough. It is wasted money making the $100 CPU in a lower end laptop faster if it costs you more both for the additional SRAM chip and amortization of the hybrid bonding capacity (not just the equivalent, but the clean room space, engineers to operate it, test equipment, reduced yield from failed bonds, etc.)

 

[Exist50]

The issues with SRAM scaling will be alleviated somewhat with GAA and BPR coming in the N2 generation, though it remains to be seen to what extent.

I'm not convinced. TSMC has been quoting what? 10% better density for N2 vs N3E? And that's 2025 earliest, and likely 2026 for AMD. So the earliest timeline for a significant increase in SRAM density would be 2026, maybe 2027. That's a looong time...

I definitely agree that SRAM scaling isn't completely dead, but it sure looks like there's plenty of inventive to move the big caches off the leading node within the next couple of years.

 

[Geddagod]

I'm not convinced. TSMC has been quoting what? 10% better density for N2 vs N3E? And that's 2025 earliest, and likely 2026 for AMD. So the earliest timeline for a significant increase in SRAM density would be 2026, maybe 2027. That's a looong time...

I definitely agree that SRAM scaling isn't completely dead, but it sure looks like there's plenty of inventive to move the big caches off the leading node within the next couple of years.

Could just be because TSMC 2nm is their first iteration past finfet so they want to be conservative. Regardless, I think AMD might just create separate dies for models with and without v-cache, low end dies without v-cache for low end products while they have high end dies with higher core counts without LLC on die at all, but rather as v-cache.

 

[Doug S]

I'm not convinced. TSMC has been quoting what? 10% better density for N2 vs N3E? And that's 2025 earliest, and likely 2026 for AMD. So the earliest timeline for a significant increase in SRAM density would be 2026, maybe 2027. That's a looong time...

I definitely agree that SRAM scaling isn't completely dead, but it sure looks like there's plenty of inventive to move the big caches off the leading node within the next couple of years.

It is pretty obvious the first cut of N2 will be pretty conservative. They seem to be planning a stepwise approach implementing GAA without scaling, then implement scaling alongside backside power and buried power rails in two additional steps. Intel thinks they can do that all in a big bang with 20A. We'll see which strategy proves more successful.

That "looong time" is a pretty short time to fully amortize the cost of a plant and equipment for a hybrid bonding process that would only be used on a massive scale during that short window. You want to add a lot to the cost of ALL AMD CPUs for a performance boost only interesting to maybe 10% of their customers.

 

[Joe NYC]

I think the big question is simply the manufacturing volume of hybrid bonding. It will take a lot of extra equipment to scale from a few niche product lines to basically everything they sell. Would make sense for that to take a few years.

But I think somewhere in the N3 generation it would make sense for them to go all-in. N3 SRAM scaling is horrible, and yet you pay the N3 premium anyway. That might be the economic incentive AMD needs.

TSMC is also scaling the capacity rapidly - on one side of the ledger.
The demand is dropping on the other side.

There was some quote from TSMC that they are scaling the SoIC capacity by factor of ~20x-30x. Starting from low numbers, we don't know what exactly it is, but it shows TSMC commitment. Stacking and hybrid bond is a tool / vehicle for TSMC to sell more wafers, so the incentive is there.

 

[Exist50]

That "looong time" is a pretty short time to fully amortize the cost of a plant and equipment for a hybrid bonding process that would only be used on a massive scale during that short window. You want to add a lot to the cost of ALL AMD CPUs for a performance boost only interesting to maybe 10% of their customers.

Oh, I'm not proposing this as just a sort term solution. Unless there's some radical change with SRAM scaling trends vs logic, then this would become the norm going forward. And I actually wasn't thinking about performance at all. The idea is that if you can move all of the L3 (and maybe L2?) to a separate die, you can actually save money vs monolithic.

Think of it this way. We're getting effectively zero SRAM area scaling from today through 2026-ish. So if AMD wants to increase on-die caches, that will directly increase area with no real way to mitigate. Personally, I don't see AMD leaving the L2 and L3 amounts untouched through Zen 5 and Zen 6. Worst case, even Zen 7 would be affected. And all the while, that SRAM is getting more and more expensive even for the same capacity.

3D V-Cache solves this, and the economics are very simple. The cost of the hybrid bonding/packaging just has to be less than the cost difference between the N and N-1 (or even N-2) processes times their respective area scalers. I see that as a very realistic possibility within a few years.

 

[Exist50]

There are patterns AMD followed so far. With Zen 1 and 3 "ground up design" translated to a restructured core where some IP blocks can be relocated from earlier designs but the whole arrangement is all new. Zen 2 and 4 were extensions, the structure is the same, "only" within the IP blocks there were changes done.

The comparison with Intel is hard as they appear to apply only the latter approach.

I don't think that's necessarily a coincidence. Intel's basically just been iterating on Core this whole time, while AMD's introduced more significant changes to its architectural approach. I think it will be very interesting to compare Lion Cove and Zen 5.