Discussion Zen 5 Discussion (EPYC Turin and Strix Point/Granite Ridge - Ryzen 8000)

[eek2121]

Zen 5 was said to be a new architecture with a grounds up design.... but so was zen 3. And yes, zen 3 was really impressive, no doubt about it, but I doubt it would be 'a new reset for CPU architecture at AMD' like zen was for them.
Personally I am expecting something like zen 3 or Golden Cove levels of increases.
But hey who knows

AMD did say as much about Zen 3, however, as moinmoin points out…

The thing about these ground up designs is not that all of the core changes, many of the blocks are still the same. Even Zen 1 did lift significant blocks from the previous construction cores. Between every gen work on blocks is done were deemed necessary and fruitful. With every even gen the blocks are optimized within the given structure, making the most of that ("picking low hanging fruits"). With every odd gen the way all those block are connected and interact is essentially reset and rethought, removing structural bottlenecks and making better use of all the blocks, and that's the big deal. That step is exactly for avoiding getting into dead ends of diminishing returns that would be the result of never touching the fundamental structure.

I 100% agree as this is usually the case. However, AMD has said Zen 5 is something new altogether. (don’t remember the exact quote)

It is quite possible they redesign the chip completely, or do something odd like introduce a new instruction set. (x86-128? 🤣) They could also just be saying this as a marketing claim like they did for Zen 3.

One thing I do know is the Zen core design has been very successful for AMD.

I do wish Microsoft, AMD, and Intel would move to eliminate legacy x86. We have emulators for that stuff now, and a full featured set of cores could be included for cases where an emulator is not appropriate. Shoot, chiplets would be perfect for that.

 

[Gideon]

I also expect the IPC uplift target to be similar to Zen 1 (which was 40%). Aggressive, yes certainly. But Intel is also taking AMD seriously this time (with the rumor of their own ground-up design) so AMD really needs to be aggressive in order to not fall behind.

I'm sure they won't mind even some ST clock regression, to achieve that . Imagine a "worst case" 40% IPC uplift coupled with a massive 20% clock-reduction (for crazy voltage ST peak on desktop). That would still mean that servers would extract nearly all of that IPC (and actually be about ~35% faster at the same power-draw at reasonable voltages). Power-constrained devices like laptops as well (as they also run on saner voltages).

Whether we like it or not. These two categories are AMD's real bread and butter. High-end Desktop and "6ghz" are very good for branding and setting the Halo effect, but I don't think anyone would even notice the lower clock speeds as long as it's still at least 20% faster in ST workloads (and obviously much more in MT).

Obviously I don't think the regression will really be anywhere near 20%, but I do think it will be there.


I really hope for an 8-wide decoder, as Intel is at 6 already, and won't be standing still. Perhaps with some nifty tricks like Tremont (thus be 4+4 in reality).

I'm also fairly confident in the "asymetric cores with the same ISA point" option, considering into what lengths AMD went to add everything but the kitchen sink to Zen 4. It would also help to compensate for the inevitable die-size bloat a much wider core would bring.

 

[DisEnchantment]

I'm also fairly confident in the "asymetric cores with the same ISA point" option, considering into what lengths AMD went to add everything but the kitchen sink to Zen 4. It would also help to compensate for the inevitable die-size bloat a much wider core would bring.

Just some thoughts.

One thing I wonder about this is that if the L3 is fully 3D stacked, underneath the core, they can put a dense CCX and high frequency CCX on top of unified L3 . Bypassing the IFOP/IOD for inter CCX CC snooping.
Current dual CCDs chips are already differing 300+ MHz in clock speed between CCD0 and CCD1 and the ACPI CPPC preferred core handling is already a thing in Windows and Linux moving the task to the fastest cores possible.
Let's say a 4.5 GHz dense CCX and 6 GHz Fast CCX which are exact instruction compatible would make the CPU very transparent to software, during all core loads the entire chip runs at 4.5 GHz anyway and during bursty ST loads the preferred core takes over. Pretty much like any 5950X or 7950X when you enable CPPC preferred core in BIOS.

Also really curious about the IFOP going away or is gonna remain, replaced by EFB or interposer things
I have seen AMD folks working on N3 GMI PHYs with double the BW of current N5 PHYs.
GMI2 --> Up to 25 Gbps SerDes, GMI3 --> 32-26 Gbps SerDes, GMI4 --> Up to 64 Gbps SerDes. Not sure what to make of that.

That is why I find the un-core really the most interesting thing to look forward to in Zen 5.
The core is like yeah 50% bigger PRF/decode/execute etc. etc. but the un-core is the total wild card.

Unfortunately there will hardly be any leaks around as usual for AMD. We have to go by some vague statements like these

"We are already heterogeneous. I can’t even think of homogenous, monolithic part going forward." - Forrest Norrod

 

[Geddagod]

Zen 5 in AMD words will be not only a completely new architecture but it will also go wider (probably in both decode and execution). So I will not base my prediction in what happened with the Zen2 to Zen 3 transition, because it should be more AMD's "Golden Cove" moment, or even more extreme than that.

Zen 3 in AMD words were ALSO a completely new architecture. Both were called a new "Ground up" architecture.
Wider is important, but AMD themselves said going wider and wider ends up having diminishing returns.

 

[Geddagod]

Just some thoughts.

One thing I wonder about this is that if the L3 is fully 3D stacked, underneath the core, they can put a dense CCX and high frequency CCX on top of unified L3 . Bypassing the IFOP/IOD for inter CCX CC snooping.
Current dual CCDs chips are already differing 300+ MHz in clock speed between CCD0 and CCD1 and the ACPI CPPC preferred core handling is already a thing in Windows and Linux moving the task to the fastest cores possible.
Let's say a 4.5 GHz dense CCX and 6 GHz Fast CCX which are exact instruction compatible would make the CPU very transparent to software, during all core loads the entire chip runs at 4.5 GHz anyway and during bursty ST loads the preferred core takes over. Pretty much like any 5950X or 7950X when you enable CPPC preferred core in BIOS.

Also really curious about the IFOP going away or is gonna remain, replaced by EFB or interposer things
I have seen AMD folks working on N3 GMI PHYs with double the BW of current N5 PHYs.
GMI2 --> Up to 25 Gbps SerDes, GMI3 --> 32-26 Gbps SerDes, GMI4 --> Up to 64 Gbps SerDes. Not sure what to make of that.

That is why I find the un-core really the most interesting thing to look forward to in Zen 5.
The core is like yeah 50% bigger PRF/decode/execute etc. etc. but the un-core is the total wild card.

Unfortunately there will hardly be any leaks around as usual for AMD. We have to go by some vague statements like these

Could be possible, but the reveal that would we be getting zen 5 vanilla and then zen 5 V-cache makes me think that any form of stacking is still too expensive for AMD without having to separately segment it. At the very least, I would expect what you are proposing would be only for some skus.

 

[moinmoin]

The core is like yeah 50% bigger PRF/decode/execute etc. etc. but the un-core is the total wild card.

That's the case for quite a long time now though. After the (glorious) change from Zeppelin to CCDs (Zen 1 to Zen 2) I was expecting more with Zen 3, but the IOD setup stayed the same. Even with Zen 4 it mostly stayed the same aside finally incorporating lessons from mobile chips as well as a minimum specification iGPU.

Let's see whether Dragon Range and Bergamo change anything about the IOD. Siena obviously will be a new smaller server IOD (right? right??). With these AMD may or may not change the uncore more and more often before Zen 5 already. We will see, I sure want more to happen in that particular area.

 

[Exist50]

That's the case for quite a long time now though. After the (glorious) change from Zeppelin to CCDs (Zen 1 to Zen 2) I was expecting more with Zen 3, but the IOD setup stayed the same. Even with Zen 4 it mostly stayed the same aside finally incorporating lessons from mobile chips as well as a minimum specification iGPU.

Let's see whether Dragon Range and Bergamo change anything about the IOD. Siena obviously will be a new smaller server IOD (right? right??). With these AMD may or may not change the uncore more and more often before Zen 5 already. We will see, I sure want more to happen in that particular area.

Considering all the changes introduced in both the desktop and server IO dies this year (DDR5, PCIe 5.0, CXL, iGPU, etc), I doubt we'll see any significant changes till Zen 6. Maybe small feature tweaks or speed bumps, but I think they'd want to reuse it for next gen.

 

[DisEnchantment]

That's the case for quite a long time now though. After the (glorious) change from Zeppelin to CCDs (Zen 1 to Zen 2) I was expecting more with Zen 3, but the IOD setup stayed the same. Even with Zen 4 it mostly stayed the same aside finally incorporating lessons from mobile chips as well as a minimum specification iGPU.

What about SH5 socket/MI300? This is a Zen 4 based product.

https://twitter.com/i/web/status/1438564239933853698

Infinity Fabric 3.0 developed for Trento made it to Genoa. From Linux patches we know Genoa has a coherent fabric to talk to GPUs and also support CXL.mem and CXL.cache. Now MI300 is a series product not one off like Trento. And we can surmise that they have the new IF v4.0 that went into that MI300 product.

When they showed this slide below it seems evident they are going to have a new Fabric to tie the AI acceleration engine to the new CPUs (which coincidentally or not happened to a key design highlight of Zen 5) and that is going to be the AIE/XDNA. And they are likely going to leverage MI300 tech to put these things together. While still a marketing slide, it seems to me the pieces of the puzzle are right there (just that there are million ways to piece them together sadly)

 

[yuri69]

Yea, AMD should move on with Zen 5. Better packaging, better interconnect => better scaling and energy/bit. Up to date machine width and depth.

Zen 2 was a shocking move with 64c Rome
Zen 3 healed the Zen 1/2 issue of 4c CCX
Zen 4 improved frequency and upped power limits

Zen 5 kinda have to bring the shiny tricks to compete. Zen 4 was lucky to compete with Golden Cove. Who knows what 2024 brings.

 

[leoneazzurro]

Zen 3 in AMD words were ALSO a completely new architecture. Both were called a new "Ground up" architecture.
Wider is important, but AMD themselves said going wider and wider ends up having diminishing returns.

In more than one interview AMD also declared that Zen5 would have been a radical departure from the current design paradigms and that it would have been something quite different from what we have seen before. Zen3 was called a new architecture already before launch, but never once a "paradigm shift".

 

[Exist50]

In more than one interview AMD also declared that Zen5 would have been a radical departure from the current design paradigms and that it would have been something quite different from what we have seen before. Zen3 was called a new architecture already before launch, but never once a "paradigm shift".

Zen 3 deserved to be called a new arch by lineage alone. If anything, perhaps more so than Zen 5.

 

[DisEnchantment]

Zen 3 deserved to be called a new arch by lineage alone. If anything, perhaps more so than Zen 5.

By this logic, Zen 5 belongs to Zen 3 family. But I can understand your perspective. Some folks have a horse in this race, some elsewhere (in fact same industry for me, and my career progression depend on our race horse performance).

But otherwise, Zen 5 is a new architecture, it has been years in development and it will deliver. Just like how Zen and Zen 3 did and as planned.
The Zen 5 program has been in the making for a long time, architecture should be frozen for quite a bit now including RTL design, high level simulations etc. The physical implementation would already be coming to a close and they would need to tape out in 1Q or 2Qs at the latest to meet the 2024 deadline.

 

[eek2121]

Considering all the changes introduced in both the desktop and server IO dies this year (DDR5, PCIe 5.0, CXL, iGPU, etc), I doubt we'll see any significant changes till Zen 6. Maybe small feature tweaks or speed bumps, but I think they'd want to reuse it for next gen.

I wouldn’t be so sure. The current monolithic die can be optimized and made more modular to reduce cost and allow for increased functionality. Right now it is a catch all for IO and is different across AMD’s product segments.

 

[Kocicak]

In more than one interview AMD also declared that Zen5 would have been a radical departure from the current design paradigms and that it would have been something quite different from what we have seen before. Zen3 was called a new architecture already before launch, but never once a "paradigm shift".

A true paradigm shift for me can mean for example abandoning the approach of a core with fixed resources and fixed number of threads it can serve, but instead having some large pool of resources, which could be dynamically assigned to tasks. If you required a few demanding threads, you could give them a lot of resources (effectivelly creating a few super powerfull "fat" cores), if you had a ton of threads, it would work as if you had a lot of compact cores serving e.g. 4 threads each.

 

[Geddagod]

Zen 3 deserved to be called a new arch by lineage alone. If anything, perhaps more so than Zen 5.

It's exactly why I think Zen 5 is another Zen 3 level change, maybe slightly higher, but nothing enormous like the 40-50% IPC gains that people are talking about. I feel like when that occurs, they will move of the zen name, at the very least for branding/marketing purposes.

 

[Geddagod]

A true paradigm shift for me can mean for example abandoning the approach of a core with fixed resources and fixed number of threads it can serve, but instead having some large pool of resources, which could be dynamically assigned to tasks. If you required a few demanding threads, you could give them a lot of resources (effectivelly creating a few super powerfull "fat" cores), if you had a ton of threads, it would work as if you had a lot of compact cores serving e.g. 4 threads each.

I agree, and I strongly believe that if Intel's "Royal Core" project is as 'paradigm changing' as it is rumored to be, then this is what they could be aiming for. Intel has certainly looked into this before- they even purchased the company that has been planning on releasing an architecture that did exactly this- Soft Machines.
However, Ian Cutress seems to think that this project seems to have been mothballed internally at Intel, maybe due to poor performance scaling or other factors, so I'm not betting on it...

 

[Exist50]

However, Ian Cutress seems to think that this project seems to have been mothballed internally at Intel, maybe due to poor performance scaling or other factors, so I'm not betting on it...

Royal or the Soft Machines stuff?

 

[Thunder 57]

A true paradigm shift for me can mean for example abandoning the approach of a core with fixed resources and fixed number of threads it can serve, but instead having some large pool of resources, which could be dynamically assigned to tasks. If you required a few demanding threads, you could give them a lot of resources (effectivelly creating a few super powerfull "fat" cores), if you had a ton of threads, it would work as if you had a lot of compact cores serving e.g. 4 threads each.

"Paradigm shift" is a phrase for eggheads who want to sound smart.

See the following:

Spoiler: Video and lyrics

Lyrics:

We must all efficiently
Operationalize our strategies
Invest in world-class technology
And leverage our core competencies
In order to holistically administrate
Exceptional synergy
We'll set a brand trajectory
Using management's philosophy
Advance our market share vis-à-vis
Our proven methodology
With strong commitment to quality
Effectively enhancing corporate synergy
Transitioning our company
By awareness of functionality
Promoting viability
Providing our supply chain with diversity (versity, ooooh)
We will distill our identity
Through client-centric solutions
And synergy (Oooooh oooh oooh)
At the end of the day (At the end of the day)
We must monetize our assets
The fundamentals of change
Can you visualize a value-added experience?
That will grow the business infrastructure and
Monetize our assets
Monetize our assets
Monetize our assets
Bringing to the table
Our capitalized reputation
Proactively overseeing
Day-to-day operations
Services and deliverables
With cross-platform innovation
Networking, soon will bring, seamless integration
Robust and scalable, bleeding-edge and next-generation
Best of breed
We'll succeed
In achieving globalization
And gaining traction with our resources in the marketplace
It's mission-critical to stay incentivized
Against this purple-poster-flexible-solutions for our customer base
If you can't think outside the box
You'll be downsized
It's a paradigm shift! (Hey, Hey! Look out!)
Well, it's a paradigm shift, now!
(Here we go! Here we go! Here we come! Here we come! Ha!)

 

[Geddagod]

Royal or the Soft Machines stuff?

The soft machine stuff, where you have a global front end and a bunch of cores, which can combine to act as larger cores while sharing resources, etc etc.
He made no comment on Royal core, if I recall correctly.
I'll try finding the reddit post I read it on later

 

[yuri69]

By this logic, Zen 5 belongs to Zen 3 family. But I can understand your perspective. Some folks have a horse in this race, some elsewhere (in fact same industry for me, and my career progression depend on our race horse performance).

But otherwise, Zen 5 is a new architecture, it has been years in development and it will deliver. Just like how Zen and Zen 3 did and as planned.
The Zen 5 program has been in the making for a long time, architecture should be frozen for quite a bit now including RTL design, high level simulations etc. The physical implementation would already be coming to a close and they would need to tape out in 1Q or 2Qs at the latest to meet the 2024 deadline.

Zen 5 somehow has to redo a lot of CCX layout like Zen 3 did. Their Zen 5 lineup reportedly consists a 256c server SKU, that's why.

Bergamo is probably done in an easy manner of two CCXes within a CCD. Still, this requires 8 of them. Reaching to 256c would require 16 dies each with 2 CCXes leading 32 separate CCXes. Merging CCXes to 16c sounds cool, but surely requires proper engineering.

 

[moinmoin]

What makes Zen 5 stand out is that it's the first ground up design under the new current AMD. Zen 1-3 were all planned and executed during AMD hardest money starved near bankruptcy years. Zen 4 is an extension of Zen 3. Zen 5 is the first design (and AM5 a platform) where AMD needn't do any compromises for financial reasons. That alone should make it a big deal.

What about SH5 socket/MI300?

Yeah, CDNA is where all the interesting uncore and package development is right now.

A true paradigm shift for me can mean for example abandoning the approach of a core with fixed resources and fixed number of threads it can serve, but instead having some large pool of resources, which could be dynamically assigned to tasks.

Such kind of "true paradigm shifts" won't happen unless they are supported by software and OSes out of the box. That alone unfortunately prevents some fundamental changes to happen. Alder Lake with its P- and E-cores, despite working out of the box, already showcases how little software is being actually optimized.

 

[Geddagod]

What makes Zen 5 stand out is that it's the first ground up design under the new current AMD. Zen 1-3 were all planned and executed during AMD hardest money starved near bankruptcy years. Zen 4 is an extension of Zen 3. Zen 5 is the first design (and AM5 a platform) where AMD needn't do any compromises for financial reasons. That alone should make it a big deal.


Yeah, CDNA is where all the interesting uncore and package development is right now.


Such kind of "true paradigm shifts" won't happen unless they are supported by software and OSes out of the box. That alone unfortunately prevents some fundamental changes to happen. Alder Lake with its P- and E-cores, despite working out of the box, already showcases how little software is being actually optimized.

Just curious, what sort of financial compromises do you think AMD did with zen that had to do with design?

 

[moinmoin]

Just curious, what sort of financial compromises do you think AMD did with zen that had to do with design?

No concrete idea! But AMD may have been short on staff, have less budget for R&D for more advanced packages, less budget for more extensive simulations of all technical possibilities etc. pp. Just keep in mind that the primary reason AMD went MCM and then chiplets while doing as few different distinct die designs across a large product range as possible wasn't because they could and for fun but because that was the only way they could afford targeting the TAM they did.

 

[Geddagod]

No concrete idea! But AMD may have been short on staff, have less budget for R&D for more advanced packages, less budget for more extensive simulations of all technical possibilities etc. pp. Just keep in mind that the primary reason AMD went MCM and then chiplets while doing as few different distinct die designs across a large product range as possible wasn't because they could and for fun but because that was the only way they could afford targeting the TAM they did.

That makes sense. I think they are going to start designing more custom dies for more specific segments, we already see examples with V-cache, but it's also really interesting how they have both 3nm and 4nm variants of zen 5.

 

[moinmoin]

That makes sense. I think they are going to start designing more custom dies for more specific segments, we already see examples with V-cache, but it's also really interesting how they have both 3nm and 4nm variants of zen 5.

Another clear difference from before is additional different core die variants as in Zen 4c/Bergamo and additional different platforms as in SP6/Siena. Maybe also mobile depending on the extend Dragon Range deviates from Raphael and Phoenix Strix deviates from the previous painter APU series. All these will continue with Zen 5 as well.