Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[moinmoin]

Does beg the question, however. With Zen 5 widely expected to bring a much "bigger" core, but only small improvements on the process side (pre-N3), then what're the implications for core counts and/or cost? Rumors seem to indicate that Turin is looking to be around 120 cores, give or take. If, for discussion purposes, we assume Zen 5 is scaled +50% from Zen 4, then that's 120/96 * 1.50 / 1.06 (N4 density gains) => 1.77x the silicon area. Pretty big growth, and it's hard to say what TSMC's wafer prices will do between now and then. But I think that unless competition forces them to cut prices, the high end chips will continue to get significantly more expensive.

Also, even if AM5 gives them some room to grow, those scalers above give roughly +40% area per core. I'm not sure they have the room to absorb that and a third compute die, but maybe with an N3 refresh they could?

I don't think we can use the current Zen 4 core size as the base there.

The transistor count increased enormously between Zen 3 and 4, but all the design changes found so far point to frugal and efficient changes, nothing that explains the huge increase. That gives credence to the possible explanation that the transistors are used to allow the now know high frequencies.

Zen 4c is planned to cut the core size to half again while retaining all features, essentially removing said transistors introduced for enabling high frequencies, alongside further optimizations.

My expectation is that Zen 5's core size will essentially build upon Zen 4c's core size. This means AMD has quite some flexibility in how to allocate and balance space and how big to make cores and CCDs. I expect them to end up at a similar size as Zen 4.

 

[DisEnchantment]

The transistor count increased enormously between Zen 3 and 4, but all the design changes found so far point to frugal and efficient changes, nothing that explains the huge increase. That gives credence to the possible explanation that the transistors are used to allow the now know high frequencies.

I find Zen 4 massive MTr gain (or at least area*scaling gain) for the achieved perf to be un impressive. But if you deep dive the published manuals thus far they are leaving no stone unturned to catch up with Intel on feature parity. 57 bit addressing, AVX512, x2AVIC and even basic things like VNMI which Intel had for a very long time. I suspect they burnt a ton of transistors there. Then there's the second GMI and 1 MiB L2. Then the new suite of SEV features which God knows when they will be disclosed. I bet IF 3.0 also burnt some MTr needed for MI300 like usecases.

What is annoying is that Zen 4 already launched and you cannot even find the manual on the dev site, what is wrong with AMD. And their Linux Merge request getting objected every time because no one can see the documentation but expected to review the code changes.

AMD's chiplets benefited more from process jumps compared to Mobile in terms of relative generational gains (albeit they start at lower MTr/mm2 ). Zen 4 chiplets got 1.82x MTr scaling vs Zen 3. To be seen if it holds true for N3, but man the heat density gonna be brutal on that node, AMD will very likely have stagnant clocks or +100MHz at best.

 

[Exist50]

Actually it is relatively speaking, because we will never really know what AMD used as baseline for DTCO for Zen 4 and what they have changed in the PDK.

While AMD might not being using N5P exactly, I think it's safe to say that they've benefitted from all the goodness it added on top of base N5. Or put another way, I don't expect AMD's intrinsic gains to be meaningfully different from the N5P->N4P shrink.

Nah... 50% is way too much, AMD is not Apple. At best I expect Zen 5 to gain 20 to 25% more transistor per core (area * scaling) or around 85mm2 CCDs (assuming they still even have CCD concept by then). Zen 3 is barely 9% MTr gain over Zen 2. N5 --> N4 is hardly any density gain. Bean counters will not allow a CCD of around 110mm2.

I definitely agree. Was proposing this as a thought exercise in response to the predictions of +20-30% IPC via increases to expensive architectural features. Typically, you'd expect to need something in the ballpark of 50% more transistors for that kind of gain. So either the gains are smaller, AMD's eating the area penalty, or they've found some clever ways to increase IPC without large increases to area.

Perhaps it's only DT and mobile Granite Ridge that we'll see N4P. Strix Point, APUs, and Turin will be on N3E. Basically, only the markets that demand the best perf/W and best density get the best node. DT is not one of those markets, especially when it's a market where people are more perf/$ sensitive. N4P would give AMD the ability to keep costs in check while raising perf/$.

My personal guess is that Zen 5c and maybe mobile will use 3nm. They probably need to stagger 4nm and 3nm development, and those seem like the markets to benefit the most from N3's particular changes (mostly low voltage/power). I don't see them developing a separate chiplet just for desktop, if nothing else.

 

[Exist50]

My expectation is that Zen 5's core size will essentially build upon Zen 4c's core size. This means AMD has quite some flexibility in how to allocate and balance space and how big to make cores and CCDs. I expect them to end up at a similar size as Zen 4.

That's an interesting proposal. So do you expect them to sacrifice frequency for IPC?

 

[moinmoin]

That's an interesting proposal. So do you expect them to sacrifice frequency for IPC?

I expect them to try to avoid having to make that choice and have both.

I'd think for Zen 4 they pulled out all stops that could hinder higher frequencies. It's essentially their first try at that which should leave plenty room for optimization. I expect them to sacrifice frequency for Zen 4c while cutting down on area but that will be a trial to still achieve high-ish frequencies. Zen 5 should then combine the lessons from both approaches, ideally achieving highs similar to Zen 4 while only spending transistors absolutely necessary for this.

So to answer your question: As a starting point, yes, I'd expect they'll first sacrifice frequency for IPC as the latter is more important for the overall design. During optimization they'll then try to achieve high frequencies again. This may fail, but so far AMD's designers had a knack for balancing compromises for great effect.

 

[Exist50]

I expect them to try to avoid having to make that choice and have both.

I'd think for Zen 4 they pulled out all stops that could hinder higher frequencies. It's essentially their first try at that which should leave plenty room for optimization. I expect them to sacrifice frequency for Zen 4c while cutting down on area but that will be a trial to still achieve high-ish frequencies. Zen 5 should then combine the lessons from both approaches, ideally achieving highs similar to Zen 4 while only spending transistors absolutely necessary for this.

So to answer your question: As a starting point, yes, I'd expect they'll first sacrifice frequency for IPC as the latter is more important for the overall design. During optimization they'll then try to achieve high frequencies again. This may fail, but so far AMD's designers had a knack for balancing compromises for great effect.

Well that's certainly a bold prediction, I'll say that! Though this is a different team than the one that created Zen 3/4, so it will be interesting to see how that manifests.

 

[DisEnchantment]

Well that's certainly a bold prediction, I'll say that! Though this is a different team than the one that created Zen 3/4, so it will be interesting to see how that manifests.

Should be the team of David Suggs (but he left AMD this year so not sure if Leslie is taking over or another architect stepped in @NostaSeronx any ideas?). Mike Clark at this point doing only architectural and design reviews. But they have 7 years (by 2024) to prepare for Zen 5. Lets see if they manage anything worthwhile in that span of time.

Zen design philosophy brought chiplet concept, Infinity Fabric, disaggregation and heterogenous compute at AMD. Until then it was all talk, not sure if anyone remembers the Fusion era at AMD during the term of Rick Bergman circa 2012
Zen concepts like Chiplets and Infintiy Fabric brought that into reality, EPYC Trento and MI300 are testament to that.

So at the very least I am expecting new design paradigms with Zen 5 and not the usual discussion of ROBs, PRF, op cycles etc.. Zen 5 is supposed to be the new reset for CPU Architecture at AMD (will have to source better info, but with AMD there is hardly any).
I am looking forward to new packaging, interconnects, disaggregation, domain acceleration, etc., beyond the usual increasing transistors, increase execute ports, etc.

 

[moinmoin]

Well that's certainly a bold prediction, I'll say that!

As I said I don't even consider it that bold. Going from Zen 4c they can double the core size without it turning out bigger than Zen 4. So it all depends on what exactly are the compromises Zen 4c has to make to achieve half of Zen 4's size. The closer to full functionality and high frequency they get there the more room Zen 5 will have to play with for additions and overhauls without increasing core size compared to Zen 4.

 

[coercitiv]

As I said I don't even consider it that bold. Going from Zen 4c they can double the core size without it turning out bigger than Zen 4. So it all depends on what exactly are the compromises Zen 4c has to make to achieve half of Zen 4's size. The closer to full functionality and high frequency they get there the more room Zen 5 will have to play with for additions and overhauls without increasing core size compared to Zen 4.

If Zen 5 is a tuned Zen 4c (in terms of transistor count focus for higher fmax), then what is Zen 5c supposed to be?

 

[Kaluan]

HWiNFO just added some early Zen5 detection/support in the newest pre-release/beta version (and a slew of Zen4/Raphael improved ones).

v7.31, Build 4880

Versions History | HWiNFO

Upcoming cahnges and version history of HWiNFO 32/64. Latest version, Upcoming changes and Full version history.

www.hwinfo.com

 

[moinmoin]

If Zen 5 is a tuned Zen 4c (in terms of transistor count focus for higher fmax), then what is Zen 5c supposed to be?

We already know that Zen 5 will be a new family, so not tuned. But while the overall core structure is being redesigned specific smaller blocks (subblocks?) are still being reused to some degree. The difference between Zen 4 and Zen 4c as I see it is similar to how server/desktop vs mobile cores were generally handled in past gens: The first implementation focuses on the implementation itself with high frequencies, the second then takes that and optimizes that for density and efficiency. Blocks are being optimized that way, when they are then reused obviously the optimized blocks would be preferred over unoptimized older ones, that doesn't make Zen 5 a tuned Zen 4c. Beside those Zen 5 will again focus on new implementations and high frequencies, with Zen 5c again optimizing those for density and efficiency. And on and on.

 

[uzzi38]

My expectation is that Zen 5's core size will essentially build upon Zen 4c's core size. This means AMD has quite some flexibility in how to allocate and balance space and how big to make cores and CCDs. I expect them to end up at a similar size as Zen 4.

Alright, I'm going to say the opposite. My expectation is that Zen 5 is going to bloat die sizes even further (as noted by Mysticial's review already - Zen 4 already dedicates die area to instructions that would otherwise normally be emulated due to the likely high transistor cost) while Zen 5 will trim most of this bloat whilst also clocking lower.

Also, given that in one of the interviews (idk which) AMD said they were targetting 6GHz for Zen 5, I'm expecting clocks to increase again as well.

 

[moinmoin]

Alright, I'm going to say the opposite. My expectation is that Zen 5 is going to bloat die sizes even further (...) while Zen 5 will trim most of this bloat whilst also clocking lower.

🤔 I tried to figure out which part you opposed so I could fix the oxymoron you included there. I failed.

You think AMD wouldn't take the lessons from Zen 4c in Zen 5 and bloat Zen 5 beyond Zen 4?

 

[Saylick]

🤔 I tried to figure out which part you opposed so I could fix the oxymoron you included there. I failed.

You think AMD wouldn't take the lessons from Zen 4c in Zen 5 and bloat Zen 5 beyond Zen 4?

I think he meant to say Zen 5c, not Zen 5, will trim most of the bloat while clocking lower.

To add to the discussion regarding Zen 5 area, I think the Zen 5 core will take up roughly the same area as Zen 4. Sure, some structures will be a lot bigger but look at what AMD accomplished with Zen 3: they literally deconstructed Zen 2 back into its building blocks, then reassembled the core such that everything was in balance again, resulting in 19% IPC for only 10% more xtors. If I am not mistaken, Zen 3 and Zen 4's backend is already plenty capable so it just needs a front end that can better feed the engine. If AMD could achieve 19% higher IPC with 10% more xtors, I think they can do >25% IPC for 15% more xtors. Take into account the slightly higher density from N4P or N3E and it more or less mitigates most of the xtor increase.

 

[moinmoin]

I think he meant to say Zen 5c, not Zen 5, will trim most of the bloat while clocking lower.

But that's in line with what I was writing about, thus my confusion.

 

[BorisTheBlade82]

Well, IIRC the Backend hasn't changed much since Zen2. There is only so much Frontend optimization you can do. So Zen5 will get wider in every way IMHO while maintaining the 8c CCD.
I would think, that starting with Zen4c both architectures will divert to a point were they will suit different server markets and Big.little as well. In the Server market Zen5 will be suited for applications were you have to pay license costs per core - thus needing strong cores. Zen5c like Zen4c is for sheer throughput - I am guessing 16c CCD with 2 CCX.
The main questions for me are: Will they change the packaging in order to fight the consumption overhead and bringing Chiplets to LP Mobile? If so how do they achieve at least 8 CCD in the server? And will they be able to squeeze 3 CCD on AM5 to make SKUs like 8+16, 8+32, 16+16?

 

[DisEnchantment]

One could argue the key enabler for future design flexibility is not core architecture or macro level details but systems architecture. Zen succeeded not mainly because of its core performance but its flexibility (Rome and Milan were not really ST champs). AMD was willing to dedicate lots of silicon area to interconnect architecture. Infinity Fabric/GMI which took a good 10% chunk of die area, systems management SMU master/slave architecture and CCM/CCS architecture were big part of that flexibility. Now you can also see how much their competitor is dedicating die area for such things ironically after talking down EPYC's glued design.

I am sure they will double down on this. Already announced IF 4.0 not sure what this entails beyond this slide.

 

[Geddagod]

Should be the team of David Suggs (but he left AMD this year so not sure if Leslie is taking over or another architect stepped in @NostaSeronx any ideas?). Mike Clark at this point doing only architectural and design reviews. But they have 7 years (by 2024) to prepare for Zen 5. Lets see if they manage anything worthwhile in that span of time.

Zen design philosophy brought chiplet concept, Infinity Fabric, disaggregation and heterogenous compute at AMD. Until then it was all talk, not sure if anyone remembers the Fusion era at AMD during the term of Rick Bergman circa 2012
Zen concepts like Chiplets and Infintiy Fabric brought that into reality, EPYC Trento and MI300 are testament to that.

So at the very least I am expecting new design paradigms with Zen 5 and not the usual discussion of ROBs, PRF, op cycles etc.. Zen 5 is supposed to be the new reset for CPU Architecture at AMD (will have to source better info, but with AMD there is hardly any).
I am looking forward to new packaging, interconnects, disaggregation, domain acceleration, etc., beyond the usual increasing transistors, increase execute ports, etc.

Zen 5 was said to be a new architecture with a grounds up design.... but so was zen 3. And yes, zen 3 was really impressive, no doubt about it, but I doubt it would be 'a new reset for CPU architecture at AMD' like zen was for them.
Personally I am expecting something like zen 3 or Golden Cove levels of increases.
But hey who knows

 

[Geddagod]

I think he meant to say Zen 5c, not Zen 5, will trim most of the bloat while clocking lower.

To add to the discussion regarding Zen 5 area, I think the Zen 5 core will take up roughly the same area as Zen 4. Sure, some structures will be a lot bigger but look at what AMD accomplished with Zen 3: they literally deconstructed Zen 2 back into its building blocks, then reassembled the core such that everything was in balance again, resulting in 19% IPC for only 10% more xtors. If I am not mistaken, Zen 3 and Zen 4's backend is already plenty capable so it just needs a front end that can better feed the engine. If AMD could achieve 19% higher IPC with 10% more xtors, I think they can do >25% IPC for 15% more xtors. Take into account the slightly higher density from N4P or N3E and it more or less mitigates most of the xtor increase.

I am not very knowledgeable in this, but I do want to add chips and cheese testing of zen 3 bottlenecks, their benchmarks had the backend of zen 3 to be a larger bottle neck than the front end of the architecture. And from what I understand, Zen 4 focused on expanding the front end, and we saw this with their IPC update breakdown in zen 4 as well, the front end changes were where the largest percentage of the IPC gain in Zen 4 was found. Lastly, unless Zen 5 is a pretty massive overhaul, I think AMD might run into the problem of diminishing returns and lack of 'low hanging fruit'. Sure zen 3 was able to increase ipc significantly without blowing up xtor count, but would zen 5 be able to follow the same pattern if many of the easy gains are already gone?

 

[moinmoin]

Zen 5 was said to be a new architecture with a grounds up design.... but so was zen 3. And yes, zen 3 was really impressive, no doubt about it, but I doubt it would be 'a new reset for CPU architecture at AMD' like zen was for them.

The thing about these ground up designs is not that all of the core changes, many of the blocks are still the same. Even Zen 1 did lift significant blocks from the previous construction cores. Between every gen work on blocks is done were deemed necessary and fruitful. With every even gen the blocks are optimized within the given structure, making the most of that ("picking low hanging fruits"). With every odd gen the way all those block are connected and interact is essentially reset and rethought, removing structural bottlenecks and making better use of all the blocks, and that's the big deal. That step is exactly for avoiding getting into dead ends of diminishing returns that would be the result of never touching the fundamental structure.

 

[leoneazzurro]

I am not very knowledgeable in this, but I do want to add chips and cheese testing of zen 3 bottlenecks, their benchmarks had the backend of zen 3 to be a larger bottle neck than the front end of the architecture. And from what I understand, Zen 4 focused on expanding the front end, and we saw this with their IPC update breakdown in zen 4 as well, the front end changes were where the largest percentage of the IPC gain in Zen 4 was found. Lastly, unless Zen 5 is a pretty massive overhaul, I think AMD might run into the problem of diminishing returns and lack of 'low hanging fruit'. Sure zen 3 was able to increase ipc significantly without blowing up xtor count, but would zen 5 be able to follow the same pattern if many of the easy gains are already gone?

Zen 5 in AMD words will be not only a completely new architecture but it will also go wider (probably in both decode and execution). So I will not base my prediction in what happened with the Zen2 to Zen 3 transition, because it should be more AMD's "Golden Cove" moment, or even more extreme than that.

 

[JustViewing]

I think people are putting too much emphasis on wider decode. Wider decode will only have limited improvement for Zen architecture. If not Intel should outright out-perform Zen. It is better to improve op-cache instead. We already seen with X3D how much memory is a bottle neck, so decode is not a bottle neck on Zen4. For integer workload I think main bottle neck is number of memory ports. Zen can only do 3 reads per cycle, with very limited x86 architectural registers there is not much possibility to improve integer IPC. So bottom line is integer execution units of Zen is not much of a bottleneck. No real world applications have 2+ IPC. IPC between Intel 12th gen and Zen4 are not that much different.

For AVX, increasing number ex-units will directly improve IPC. Even more so with AVX512 and its 32 registers. Many AVX code run in a loop, so instruction can be served from op-cache without widening the decode.

 

[leoneazzurro]

AMD itself said they would have gone wider and that Zen 5 would have been a radical departure from current Zen architecture. So, until we have details proving the opposite, I'd say it's wrong to make assumptions on Zen 5 based on what the current Zen architecture is.

 

[inf64]

Since they will go wider on the front and back end, they must have invested in techniques that will extract the most ILP (instruction level parallelism) from the bigger Zen 5 core. I expect a similar 40-50% IPC target versus Zen 3 (new core => new core). Let's hope clock speeds will be unaffected.

 

[movdx]

What shall we expect in terms of mobile performance?