Discussion Zen 5 Discussion (EPYC Turin and Strix Point/Granite Ridge - Ryzen 8000)

[Ajay]

I hope for 12core chiplet for Zen5. If there will be 24core chip and stick to same clocks as Zen4, that will be the one i replace my 7950x with in the future.

That would make sense to me. 12 cores is about the max for ring archs. They require additional nodes for memory and IO. It’s sort of like token ring networks, at each node has a tag has to be read and a determination whether this is the correct node, or if it has to be retransmitted and forwarded further down the ring. They latency really starts adding up and becomes too variable above that number (total ~ 14 nodes).

Low frequency Zen4c like chiplet (with Zen5 ISA) would make a great upper tier Zen5 SoCs with P&E architecture. (Zen5c chip let’s could be scavenged dice that weren't suitable for low power server use - maybe 12 cores).

I know Clark and Papermaster were excited to talk about Zen5 just after Zen4 came out. Something exceptional must must be coming out if they talked about it that soon after a major launch.

 

[moinmoin]

I know Clark and Papermaster were excited to talk about Zen5 just after Zen4 came out. Something exceptional must must be coming out if they talked about it that soon after a major launch.

I know following's being repeated, bear with me: Anything less than exceptional for Zen 5 would frankly be a disappointment. The reason is that Zen 1 through 3 were all planned and mainly executed during the time AMD was bordering bankruptcy. Zen 4 is an extension of Zen 3 which limits the kind of changes applicable. Zen 5 is the first all new core family that started when AMD was in financially safe waters again, so with access to resources the teams working on especially Zen 1 and 2 could only dream of. This should make a huge difference.

 

[TESKATLIPOKA]

I know following's being repeated, bear with me: Anything less than exceptional for Zen 5 would frankly be a disappointment. The reason is that Zen 1 through 3 were all planned and mainly executed during the time AMD was bordering bankruptcy. Zen 4 is an extension of Zen 3 which limits the kind of changes applicable. Zen 5 is the first all new core family that started when AMD was in financially safe waters again, so with access to resources the teams working on especially Zen 1 and 2 could only dream of. This should make a huge difference.

Just because AMD had more money when they started designing Zen5 doesn't mean It would end up exceptional.

What would be even considered as exceptional for Zen5?
+40% ST and +100% MT in CBR23 for example?

For comparison: Zen3 5700x (65W) vs Zen4 7700(65W)
CB R23 ST: 1538 vs 1916 (+25%)
CB R23 MT: 13660 vs18720 (+37%)

Increasing MT performance is relatively easy to do, but that ST performance will be very hard.
We can't expect much higher clocks, but 6GHz should be doable, that's ~6% higher performance.
The rest has to come from IPC and 32% higher IPC is a lot to ask for If we want ~40% better ST performance.
Just the core size would increase significantly, but better process should compensate.
If IPC is only 20% better, then ST performance will improve by only 27%, which is comparable to what we saw with Zen4. So nothing exceptional.

For better MT, AMD just needs to add 50% more cores + 20-32% better IPC and you are at +80-98% higher MT performance If clocks stay the same.

The question is how would CCX(CCD) look like.
AMD can opt for 6x Zen5 + 6x Zen4c or be more aggressive and go for 8x Zen5 + 8x Zen4c per CCX(CCD). I would keep L3 at 32-36 MB, no reason for more when cache scaling is already an issue with 5nm process.

CCD	die size (measured)	Uncore size	L3 size	Core + L2 + power banks size	die size (calculated)
Zen3	80.72 mm2 7nm	11.22	35.52	8 * 4.11	79.62 mm2
Zen4	70.74 mm2 5nm	12.19	25.10	8 * 3.84	68.01 mm2
Zen4 12C Zen4 36MB L3	~88 mm2 5nm	12.19	28.24	12 * 3.84	86.51 mm2
Zen4 16C Zen4 32MB L3	~100 mm2 5nm	12.19	25.10	16 * 3.84	98.73 mm2

I can't tell how big this 12-16C Zen5+4c CCD on 3nm would be, but It shouldn't be bigger than 12-16C Zen4 version on 5nm process.

I think we can expect significantly better MT, but I am pretty sceptical about ST being higher than 20-25%.

 

[Henry swagger]

Just because AMD had more money when they started designing Zen5 doesn't mean It would end up exceptional.

What would be even considered as exceptional for Zen5?
+40% ST and +100% MT in CBR23 for example?

For comparison: Zen3 5700x (65W) vs Zen4 7700(65W)
CB R23 ST: 1538 vs 1916 (+25%)
CB R23 MT: 13660 vs18720 (+37%)

Increasing MT performance is relatively easy to do, but that ST performance will be very hard.
We can't expect much higher clocks, but 6GHz should be doable, that's ~6% higher performance.
The rest has to come from IPC and 32% higher IPC is a lot to ask for If we want ~40% better ST performance.
Just the core size would increase significantly, but better process should compensate.
If IPC is only 20% better, then ST performance will improve by only 27%, which is comparable to what we saw with Zen4. So nothing exceptional.

For better MT, AMD just needs to add 50% more cores + 20-32% better IPC and you are at +80-98% higher MT performance If clocks stay the same.

The question is how would CCX(CCD) look like.
AMD can opt for 6x Zen5 + 6x Zen4c or be more aggressive and go for 8x Zen5 + 8x Zen4c per CCX(CCD). I would keep L3 at 32-36 MB, no reason for more when cache scaling is already an issue with 5nm process.

CCD	die size (measured)	Uncore size	L3 size	Core + L2 + power banks size	die size (calculated)
Zen3	80.72 mm2 7nm	11.22	35.52	8 * 4.11	79.62 mm2
Zen4	70.74 mm2 5nm	12.19	25.10	8 * 3.84	68.01 mm2
Zen4 12C Zen4 36MB L3	~88 mm2 5nm	12.19	28.24	12 * 3.84	86.51 mm2
Zen4 16C Zen4 32MB L3	~100 mm2 5nm	12.19	25.10	16 * 3.84	98.73 mm2

I can't tell how big this 12-16C Zen5+4c CCD on 3nm would be, but It shouldn't be bigger than 12-16C Zen4 version on 5nm process.

I think we can expect significantly better MT, but I am pretty sceptical about ST being higher than 20-25%.

How many design teams does amd have ?

 

[DisEnchantment]

Just because AMD had more money when they started designing Zen5 doesn't mean It would end up exceptional.

Like RDNA3, which was such a waste of all those awesome perf charts which you worked on so much day after day

What would be even considered as exceptional for Zen5?
+40% ST and +100% MT in CBR23 for example?

Efficiency? Scalability? Flexibility?

For comparison: Zen3 5700x (65W) vs Zen4 7700(65W)
CB R23 ST: 1538 vs 1916 (+25%)
CB R23 MT: 13660 vs18720 (+37%)

Increasing MT performance is relatively easy to do, but that ST performance will be very hard.
We can't expect much higher clocks, but 6GHz should be doable, that's ~6% higher performance.
The rest has to come from IPC and 32% higher IPC is a lot to ask for If we want ~40% better ST performance.
Just the core size would increase significantly, but better process should compensate.
If IPC is only 20% better, then ST performance will improve by only 27%, which is comparable to what we saw with Zen4. So nothing exceptional.

They would need to beat Zen 4 perf increase at the very least. There must be a good reason Mike Clark is excited about Zen 5 when Zen 4 is not even launched.

At the very least N5 --> N3E should yield as much perf as the N7 --> N5 transition if not better.



I think they will improve frequency minimally, but claw back a lot of efficiency, which would be absolutely needed in case of bigger cores. But 5% perf they can manage which would put 6GHz+ easy in range (5.7 * 1.05 = ~ 6GHz, in fact my 7950X can boost to 5.88 GHz, on GB ST).
Zen 4 CCD has an abysmally low density for N5 at ~93 MTr/mm2. The thermal hotspot also is a constraint.

 

[igor_kavinski]

so with access to resources the teams working on especially Zen 1 and 2 could only dream of. This should make a huge difference.

By resources, do you mean engineers? They can't increase the number of engineers too much because then the effort in communication and co-ordination between them becomes a substantial overhead. I remember that Jim Keller said that one of his guiding principles was to limit the number of people in teams. I think the resources argument is kind of moot because humans tend to work best within constraints. Giving a bunch of engineers whatever they need may make them lazy and complacent and overconfident. A balance has to be struck. With how AMD has been struggling to execute flawlessly lately, it seems the influx of cash isn't making things better. I think servers is the only space where we haven't heard any negative reports of AMD stumbling recently. Whoever is in charge of that division, they need more of them.

 

[uzzi38]

Like RDNA3, which was such a waste of all those awesome perf charts which you worked on so much day after day


Efficiency? Scalability? Flexibility?


They would need to beat Zen 4 perf increase at the very least. There must be a good reason Mike Clark is excited about Zen 5 when Zen 4 is not even launched.

At the very least N5 --> N3E should yield as much perf as the N7 --> N5 transition if not better.

View attachment 74924

I think they will improve frequency minimally, but claw back a lot of efficiency, which would be absolutely needed in case of bigger cores. But 5% perf they can manage which would put 6GHz+ easy in range (5.7 * 1.05 = ~ 6GHz, in fact my 7950X can boost to 5.88 GHz, on GB ST).
Zen 4 CCD has an abysmally low density for N5 at ~93 MTr/mm2. The thermal hotspot also is a constraint.

That's assuming the Zen 5 CCD uses N3E.

 

[TESKATLIPOKA]

Like RDNA3, which was such a waste of all those awesome perf charts which you worked on so much day after day

You are right, they were awesome until we saw the cruel reality.

Efficiency? Scalability? Flexibility?

This doesn't tell me much, and I think these were also true for Zen4.

They would need to beat Zen 4 perf increase at the very least. There must be a good reason Mike Clark is excited about Zen 5 when Zen 4 is not even launched.

At the very least N5 --> N3E should yield as much perf as the N7 --> N5 transition if not better.

View attachment 74924

I think they will improve frequency minimally, but claw back a lot of efficiency, which would be absolutely needed in case of bigger cores. But 5% perf they can manage which would put 6GHz+ easy in range (5.7 * 1.05 = ~ 6GHz, in fact my 7950X can boost to 5.88 GHz, on GB ST).
Zen 4 CCD has an abysmally low density for N5 at ~93 MTr/mm2. The thermal hotspot also is a constraint.

Yeah, Mike Clark was very optimistic about Zen5 in that Anandtech interview. He even said he can't wait to buy one, but It's not like he was comparing It to Zen4.
What I know is that we can't expect much performance from frequency. IPC has to increase significantly.

 

[TESKATLIPOKA]

That's assuming the Zen 5 CCD uses N3E.

If AMD will still use N4, then I don't think we can expect big increases.

 

[DisEnchantment]

That's assuming the Zen 5 CCD uses N3E.

If AMD will still use N4, then I don't think we can expect big increases.

"You should expect to see , you know, 4nm and 3nm versions of Zen 5 and you will see them in 2024" - Lisa Su

They already said, N3 and N4 for Zen 5. Also from LinkedIn, some engineers were mentioning 64 Gbps GMI on N3.

But 3D stacking would be more mature on N4 I guess at beginning of 2024

 

[igor_kavinski]

"You should expect to see , you know, 4nm and 3nm versions of Zen 5 and you will see them in 2024" - Lisa Su

Exciting stuff! But almost two years away since it's gonna be more Q4 2024

 

[Tigerick]

Exciting stuff! But almost two years away since it's gonna be more Q4 2024

Should be H1 next year cause STX and Turin lineup with Zen 5 core are expected before Q2 next year...

 

[igor_kavinski]

Should be H1 next year cause STX and Turin lineup with Zen 5 core are expected before Q2 next year...

Not holding my breath for that but yeah, that would be really nice if it happens.

 

[Tigerick]

Not holding my breath for that but yeah, that would be really nice if it happens.

Yeah, timings are tight especially AMD has to fight with Apple and Intel to get allocation of N3B/E nodes. That is why I think desktop and server version of Zen5 cores will use N4P process. Only STX lineup are mostly based on N3E

 

[Tigerick]

If AMD will still use N4, then I don't think we can expect big increases.

AMD could further enhance Zen5 core architecture, adding more cores (I expect double cores ) and bundle V-cache as standard. So still pretty headroom to go...

 

[igor_kavinski]

bundle V-cache as standard

I don't see that happening. It's not an easy process and they have limited manufacturing capacity to do that. Plus, they have their server obligations which will further prevent them for flooding the market with affordable V-cache CPUs.

 

[DisEnchantment]

AMD has to fight with Apple and Intel to get allocation of N3B/E nodes.

There is going to be too much capacity.

TSMC did not actually start the F12P9 meant for Intel, only F12P8. Intel have cut orders.
Plenty of N3 is there by beginning of 2024. F18P5/6/7 are for N3 and F18P4 also was doing N3 as well during risk production in 2022. And by 2H24 Fab18P8 will be online.
No more expansion for N3 and TSMC is actually starting to build N2 fabs now, they already have clearance to build behind the Fab12P9 in Hsinchu.

 

[Tigerick]

I don't see that happening. It's not an easy process and they have limited manufacturing capacity to do that. Plus, they have their server obligations which will further prevent them for flooding the market with affordable V-cache CPUs.

The current V-Cache are manufactured by N6 process, which has ample production capacity by now. That's why no more shortage of PS5 (PS5's SoC are made by N6 process).

Another reason that I believe Zen 5 has double cores count cause Turin will double the cores from 96 cores to 192 cores with same socket SP5. (Bergamo Next with Zen 5C will have even more) That's mean with maximum of 12 CCDs, each CCD contains 16 cores Zen5. So unless AMD screw things up, Zen5 would be big upgrade for AM5 platform.

 

[Tigerick]

There is going to be too much capacity.

TSMC did not actually start the F12P9 meant for Intel, only F12P8. Intel have cut orders.
Plenty of N3 is there by beginning of 2024. F18P5/6/7 are for N3 and F18P4 also was doing N3 as well during risk production in 2022. And by 2H24 Fab18P8 will be online.
No more expansion for N3 and TSMC is actually starting to build N2 fabs now, they already have clearance to build behind the Fab12P9 in Hsinchu.

Thanks for insights info. As for Intel cutting order, Intel might have last minute rush orders this year because I "believe" in IFS to serve productions of GNR, SF and ARL.

As for more mainstream N3E nodes, I expect Qualcomm, NV, Mediatek and AMD will be interested due to competition reasons. We will see how the things turnout.

 

[TESKATLIPOKA]

I am starting to consider waiting for Strix Point, If It's using 3nm and has 12-16 cores + 20-24CU IGP.

I will buy 64GB DDR5, set 16GB for IGP and will laugh at anyone who bought N33, Ada107 or Ada106 with only 8GB Vram.

 

[igor_kavinski]

The current V-Cache are manufactured by N6 process, which has ample production capacity by now.

The V-cache die is not the limitation. The bonding process is. I read somewhere that currently TSMC has a production limit of about 30K V-cache CPUs per month. Has there been any progress in increasing that rate?

 

[Tigerick]

Hi guys, since STX1 should move to chiplets design, there are some discussions on which solutions AMD will employ. Thus I have listed 3 designs with pro and cons.

Cyan color indicates N3E process whereas orange color means N4 process. AMD should use 2 x MCD, each containing 16MB IC and supporting 32-bit x 2 LPDDR5x-8533 memory controller.

I created 2 versions of RDNA3+ cause there was rumors of 24 CU with 1536SP. That means STX1 will have 18TF . I have doubts but Intel is rumored to have 320EU with 2560ALU in the works so AMD may need to response

See for yourself and let me know what you think AMD will employ. If you have other ideas, do let me know...

Oh yeah, I use PHX1 base as scale: 178mm2 die size. N3E no doubt have higher density but STX has 8 Zen 5 cores and 4 Zen 4C (plus 4MB L3 cache?), RDNA3+ and other improvement. For the sake of comparison, let's use 178mm2.

RDNA3+ 768SP (1536ALU)	Pros and Cons	RDNA3+ 1536SP (3072ALU)
	Derived from desktop 7000 CPU CCD contains CPU with L3 cache IOD contains graphics, AIE and FCH Small CCD saves cost IOD can get pretty big with more features like double the SP of graphics
	Diagram leaks by RGT CCD contains CPU + IOD GCD contains graphics only CCD die is comparable big GCD can have multiple sizes AMD could change graphics GCD depends on competition GCD with 1536SP will draw more power. My estimate would be addition of 10-15W That's why AMD will create monolithic version of STX2 to cater ultraportable market
	Wild speculation: In 2025, STX+ RDNA4 with 1536SP Half of SP of N43 With N3E, GCD should consume lower power than STX version
	All in one cores with external cache + memory controllers Almost like 3nm version of M2 Pro with IC BOM will be highest Lack of flexibility

 

[Tigerick]

I am starting to consider waiting for Strix Point, If It's using 3nm and has 12-16 cores + 20-24CU IGP.

I will buy 64GB DDR5, set 16GB for IGP and will laugh at anyone who bought N33, Ada107 or Ada106 with only 8GB Vram.

You might need to wait until 2025 for such configuration to happen

 

[Mopetar]

Yeah, Mike Clark was very optimistic about Zen5 in that Anandtech interview. He even said he can't wait to buy one, but It's not like he was comparing It to Zen4.

Well he's not going to say it's a pile of hot garbage or anything other than he's excited about. I wouldn't read too much into his statements beyond it's what he's going to say regardless of what the product looks like.

Even grand designs that look good on paper can fall short for any number of reasons. Look at RDNA3 which supposedly had a serious flaw discovered late into production.

Assuming that AMD is doing some major work on the front end, a big performance uplift is certainly possible because if they're able to dispatch more micro-ops per cycle, it's not too difficult to increase the number of execution units to take advantage of the more capable front-end.

 

[eek2121]

I wouldn’t mind a frequency regression if it meant improved efficiency, but I doubt AMD will willingly drop frequencies. Many people still look at clock speed to this day as an indicator of performance.

Honestly AMD could simply double up the cores and widen certain parts of the architecture a bit and they would likely have a competitive chip.