Discussion Zen 5 Discussion (EPYC Turin and Strix Point/Granite Ridge - Ryzen 8000)

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DisEnchantment

Golden Member
Mar 3, 2017
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Well, since many folks already got their hands (or at least going to get) on Zen 4 CPUs , time to discuss about Zen 5 (Zen 4 already old news :D)

We already got roadmaps and key technologies like AIE
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Some things we already knew
  • Dr. Lisa Su and Forrest Norrod already mentioned at FAD 2022 on May 9th, during Q&A that Zen 5 will come in N3 and N4/5 variants so it will be on multiple nodes.
  • Mark Papermaster highlighted that it will be a grounds up architecture, Also mentioned last para here
  • Mike Clark mentioned that they started to work on Zen 5 already in 2018. This means Zen 5 by the time it launches would have been under conception and planning and development for much longer than the original Zen program
For a CPU architecture launching in early 2024 in the form of Strix Point for OEM notebook refresh, tape out should be happening in the next few months already.
Share your thoughts


"I just wanted to close my eyes, go to sleep, and then wake up and buy this thing. I want to be in the future, this thing is awesome and it's going be so great - I can't wait for it." - Mike Clark
 
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Fjodor2001

Diamond Member
Feb 6, 2010
3,688
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no.
AMD isn't spamming dense in client DT.
No, they'll have an actual LITTLE to do the low-power island thing
So big.LITTLE, and thus Zen 5P & 5E on DT, after all.

Like I said previously, it was bound to happen, but AMD was just a little late the party after everyone else in the business already did it (Apple, Qualcomm, Intel, ...).

Now we'll just have to see what AM5 Zen5 SKUs there will be, e.g.:
* 2x8P
* 1x16P
* 2x16P
* 8P+16E
* 2x16E
* 8P+2x16E
* ...

It's still unclear if the 16C CCX:es will only be for E or P cores for Zen5. I.e. if there'll be any 16P CCX, or only 8P CCX and 16E CCX.
 

adroc_thurston

Golden Member
Jul 2, 2023
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So big.LITTLE, and thus Zen 5P & 5E on DT, after all.
No.
Like I said previously, it was bound to happen, but AMD was just a little late the party after everyone else in the business already did it (Apple, Qualcomm, Intel, ...).
No.
Now we'll just have to see what AM5 Zen5 SKUs there will be, e.g.:
* 2x8P
* 1x16P
* 2x16P
* 8P+16E
* 2x16E
* 8P+2x16E
NO.
It's still unclear if the 16C CCX:es will only be for E or P cores for Zen5. I.e. if there'll be any 16P CCX, or only 8P CCX and 16E CCX.
NO. Just no.
The LITTLE in question is a Cat-core style sub 600mW thingy designed for 4c cluster low power operation.
 

DisEnchantment

Golden Member
Mar 3, 2017
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Looking at this again it, vs Z4
  • +2 rename/dispatch
  • +2 ALUs
  • +1 LD/cycle
  • 512b FP width
  • 64B LD/ST queues
  • 48K L1D
  • OOO structures increased
  • Usual generational architectural improvements scattered around
  • New BP with larger BTBs -> zero bubble conditional branches sounded like the patent I listed before where a second BP scans the other conditional branch
  • Decode width unknown, doubtful it is going to be beyond 6 wide if at all they even increase.
  • uop cache unknown
  • "2 basic block fetch" --> Does this mean 2x fetch and decode blocks akin to Tremont?
Does not seem terribly bloated, would have indeed seems akin to the Z2 -> Z3 evolution. The unknowns however do seem like the kind of big ticket items. I think the zero bubble conditional branch could be tied to the "2 basic block fetch".

Low Power core
  • Probably the low power core option is not having 512b FP pipes or 64B LD/ST queues (they mentioned FP 512 variants, which would mean 512 pipes and data structures not standard across all core)
  • Denser node/efficiency optimized libs as usual
  • Cache reduction as usual
  • If the 2x basic block fetch is akin to what I described, they could clock gate the second fetch block aggressively for mobile
However a major departure from Zen 3/4 series are the unified schedulers for INT and FP back to Zen 2 style. Would be interesting to see latencies with Zen 5.

It seems to me for now (for lack of more info), the answer is this itself, the 2 basic block fetch is related to the zero bubble branch predictor.
The BP can fetch two blocks. For the taken and not taken branch. When there is high confidence the other branch is not fetched.
In case the BP confidence is low the decode width or uop/cycle needs to be higher in order feed enough uops for both branches.
The BTBs need a big upgrade. And the Retire Queue and other OOO needs a big bump too.

So definitely wider decode, I would guess 6 at least.

Very ambitious core. It will shine (or might not as well, a la Bulldozer). One thing for sure it will burn much more power.

For such a radical design, I would expect a lot more than 15% gain to be worth the risks and power usage and not to mention possible security implications.
 

Frenetic Pony

Senior member
May 1, 2012
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I just noticed that in the slide below, for Nirvana it says "Low power core option". Notice that this is different naming compared to for Persephone where it says "Dense option".

Any thoughts on this?

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Thoughts are this looks 3 years old and is probably a bit out of date.

That being said, it'd be interesting to see if they did go for a different core design, seems to work well for Apple and their ridiculously efficient low power cores. Or we could see what Intel did with their new "Double E" or whatever they're calling it, the pair of E cores in Meteor lake that are on the I/O tile and tweaked to run at lower voltage.
 

blackangus

Member
Aug 5, 2022
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I am likely going to get Zen5, so wondering if there were going to be new chipsets/motherboards, like previous generations on AM4. Currently still on an AM4 socket MB. If not I may try to just grab a current AM5 MB on the blackfriday deals.
But if there were new MB's coming I would just wait and get the latest and greatest when Zen5 becomes available.
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
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Sure but we had x370(2017),x470(2018),x570(2019), was not really sure if we were due for an 770 aligned with zen5 as last socket debut had consecutive years of new chipsets.
I don't remember exactly what the changes were, but for example, PCIE 2, PCIE3, and PCIE4 . At least 3 and 4 were in these. at first, you needed a new chipset for a new Zen version, like 570 for Zen 3, but eventually I think all 3 now support all 1,2,3 generations. So at the time they were needed but after bios updates, its just feature set. Zen 4 to Zen 5 brings nothing that I am aware of unless it supports PCIE 5.0.
 

blackangus

Member
Aug 5, 2022
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Could be alot of things (smaller process, more features, more cost effective, etc). Zen4 to Zen5 doesn't appear to have more PCIE support, but there are features that are chipset side that dont depend on the processor as well!.
Not saying we need one , but if there is one expected then Ill get the latest and greatest.
 
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mikk

Diamond Member
May 15, 2012
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Thoughts are this looks 3 years old and is probably a bit out of date.

That being said, it'd be interesting to see if they did go for a different core design, seems to work well for Apple and their ridiculously efficient low power cores. Or we could see what Intel did with their new "Double E" or whatever they're calling it, the pair of E cores in Meteor lake that are on the I/O tile and tweaked to run at lower voltage.


At the bottom it says 2023. Looks fairly new to me.