Discussion Zen 5 Discussion (EPYC Turin and Strix Point/Granite Ridge - Ryzen 8000)

[DisEnchantment]

Well, since many folks already got their hands (or at least going to get) on Zen 4 CPUs , time to discuss about Zen 5 (Zen 4 already old news )

We already got roadmaps and key technologies like AIE








Some things we already knew

• Dr. Lisa Su and Forrest Norrod already mentioned at FAD 2022 on May 9th, during Q&A that Zen 5 will come in N3 and N4/5 variants so it will be on multiple nodes.
• Mark Papermaster highlighted that it will be a grounds up architecture, Also mentioned last para here
• Mike Clark mentioned that they started to work on Zen 5 already in 2018. This means Zen 5 by the time it launches would have been under conception and planning and development for much longer than the original Zen program

For a CPU architecture launching in early 2024 in the form of Strix Point for OEM notebook refresh, tape out should be happening in the next few months already.
Share your thoughts

"I just wanted to close my eyes, go to sleep, and then wake up and buy this thing. I want to be in the future, this thing is awesome and it's going be so great - I can't wait for it." - Mike Clark

 

[H433x0n]

It’s discussions like these that I wish @adroc_thurston wasn’t on a temp ban.

I tend to believe that the IPC increase is likely in the 25-30% range for a few reasons. Anything less than this would make a frequency trade off a dubious proposition. Turin also seems to increase power consumption iso core by a small amount when going by the basic specifications.

 

[Ajay]

It’s discussions like these that I wish @adroc_thurston wasn’t on a temp ban.

I tend to believe that the IPC increase is likely in the 25-30% range for a few reasons. Anything less than this would make a frequency trade off a dubious proposition. Turin also seems to increase power consumption iso core by a small amount when going by the basic specifications.

How did he get banned?

 

[PJVol]

Rumours of 200-300MHz regressions, but this cant be in MT since that s about impossible, it can only apply to ST if ever it s confirmed.

There's still no point in ST limitation - not a single reason except going beyond FIT threshold, whereas all-core clocks are always boils down to predetermined infrastructure (tdp, edc, thermals) and/or process (fit, Fmax) limits.

 

[H433x0n]

How did he get banned?

Interjecting Zen 5 stuff into an Intel thread (presumably repeatedly). I think it’s just temporary. I feel bad about it since he was arguing with me at the time.

 

[Abwx]

There's still no point in ST limitation - not a single reason except going beyond FIT threshold, whereas all-core clocks are always boils down to predetermined infrastructure and/or process limits.

All core clock being quite lower than ST core clock they can benefit from a more efficient process either to increase slightly frequency or to keep the same frequency but at forcibly better perf/watt.

 

[eek2121]

View attachment 86136

With all the chatter of frequency regression with Zen 5, a 300-400 MHz frequency regression would make it the weakest improvement for a Zen generation ever even with a fat 25% IPC gain. They have to keep same clocks otherwise the would need an impossibly high 35%+ IPC gain just to match the Zen 4 perf gains.
Doubtful Zen 5 can repeat the ~27% ST perf gain of Zen 4 with a clock regression. Couple that with FCLK plateauing from supposed 'same IOD' rumors.

On the other hand, at lower clocks efficiency should be greatly improved.

I would take rumors of a a frequency regression with a grain of salt. Even if there is one, AMD will likely more than make up for it in terms of IPC.

What you have to understand is that thanks to core power states, frequencies are already not straightforward to begin with. Sure, Zen 4 can hit 5.85ghz, but if you open up hwinfo you will notice that core effective clocks will almost never be that high, meaning these chips are being extremely aggressive about switching to lower power states.

Zen 5 could very well hit 6ghz. That does not mean it will do so continuously under heavy load.

I said at isoprocess.




Not sure about this, Zen 3 use more power at same frequency than Zen 2 but with 5% lower frequency you can reduce power much more than you lose perfs.


Scaling has nothing to do with TDP unless the 16 first threads (for a 7950X) exhaust all the power budget, but that s not the case, in CB the SMT gain is about 30%, at a given frequency you ll have 30% more throughput than with 16T,instead you use those 30% power budget to boost the 16 first threads frequency instead the uplift would be miserable comparatively.

Zen 3 uses a bit more power at the same frequency, but it is also significantly faster. Zen 3 has a much higher perf/watt than Zen 2 for ANY given frequency.

Zen 5 will be the same as Zen 4.

Personally I am hoping for a 40-50% IPC increase. Wasn’t Zen 1 a 52% increase over bulldozer?

 

[TESKATLIPOKA]

Personally I am hoping for a 40-50% IPC increase. Wasn’t Zen 1 a 52% increase over bulldozer?

Bulldozer was so bad that It was easy for Zen 1 to have 52% higher IPC.

 

[DisEnchantment]

Which makes rumors of clock regression a bit odd since N4P should improve efficiency, allowing a wider/deeper core to stay within similar power/thermal constraints considering Z4 was already designed for really high frequencies from design and process perspective (esp customization of the metal layers)

Z3 increased power usage per Core vs Z2 at iso frequency but it clocked higher, thanks to newer boost and scaling algorithm, more process optimizations it manage to clock even higher while remaining on same N7.

How much wider/deeper would it have to be to get a clock regression considering there are uarch improvements for efficiency and node improvements.

On a side note, choice of N4P seems sound considering N4P->N3B jump to be very minor from efficiency point of view.

 

[Geddagod]

I said at isoprocess.

Even iso process, that's just poor design if that ends up happening tbh

Not sure about this, Zen 3 use more power at same frequency than Zen 2 but with 5% lower frequency you can reduce power much more than you lose perfs.

ISSCC 2021? Whatever year AMD did their Zen 3 presentation

Scaling has nothing to do with TDP unless the 16 first threads (for a 7950X) exhaust all the power budget, but that s not the case, in CB the SMT gain is about 30%, at a given frequency you ll have 30% more throughput than with 16T,instead you use those 30% power budget to boost the 16 first threads frequency instead the uplift would be miserable comparatively.

?

 

[Timorous]

Interjecting Zen 5 stuff into an Intel thread (presumably repeatedly). I think it’s just temporary. I feel bad about it since he was arguing with me at the time.

To be honest it was circling the 'how strong is the Intel roadmap discussion' anyway so I think it was a poor decision given the context of the back and forth.

 

[yuri69]

Personally I am hoping for a 40-50% IPC increase. Wasn’t Zen 1 a 52% increase over bulldozer?

52% increase vs Excavator. Excavator is a L3-less Bulldozer variant - converted to a mobile-first project.

The Excavator core still carries the burden of Family 15h - narrow core, odd frontend, bad cache setup, horrible edge case behavior, no uop cache, etc. Zen 1 is a standard "modern" core learning from Intel's Haswell and later designs.

Extracting ILP is fun, but doing so in a core design scaling form 15W SKUs and targeting 6GHz is a bit different situation than Excavator vs "standard x86 core".

Frankly, the math is not that easy since Zen 4 gains are often not really close to those 25+%.

 

[Fjodor2001]

It’s discussions like these that I wish @adroc_thurston wasn’t on a temp ban.

Did not know he was temporarily banned, but it's cases like this I'm kinda glad he is so other opinions can be discussed without being drowned.

 

[PJVol]

All core clock being quite lower than ST core clock they can benefit from a more efficient process either to increase slightly frequency or to keep the same frequency but at forcibly better perf/watt.

Or they were unable to optimize the arch-driven Cac increase enough to keep all-core clocks at Zen 4 level, even taking into account 4nm node PPA advantage, so a slight reduction in MT clocks seems reasonable and quite expected.
I'm afraid no more massive Cac optimizations aka Zen2->Zen3

 

[H433x0n]

On a side note, choice of N4P seems sound considering N4P->N3B jump to be very minor from efficiency point of view.

It’s a cruel twist of fate that when Intel decided to lean into using TSMC silicon for some of their desktop products that they got stuck with N3B.

From the A17 tests the jump from N5P -> N4P had more perf/watt improvements than N4P -> N3B. That’s what Geekerwan’s Spec2017 tests showed at least.

So it definitely worked out in AMD’s favor going with N4P for Zen 5.

 

[SpudLobby]

Hmm, guess this is the Zen 5's true picture, not as revolution as people claimed. So much for hype around here . So now we are expecting same 16-core Zen5 without changes on IOD (no changes on graphics engines and no AIE as well), how much prices are we willing to pay??? Definitely not $999

Better yet, AMD should revise pricing on the Zen5's lineup, what is the points of buying Zen5 if X3D version of Zen3 and 4 is cheaper and faster in gaming??? Furthermore, gamers are expecting X3D version of Zen5 half a year later. In my opinion, AMD should replace standard Zen5 with X3D version, maybe left standard 6-core version as sub-$300 CPU...

I am not sure about power efficiency of Zen5, since it is based on N4P process, maybe Zen6 will change that???

I din’t see how this isn’t a huge jump. The power at a given performance level is going to be lower via lower clocks and a wider arch unless AMD really blows it. It won’t be crazy but it’ll be an improvement

 

[Doug S]

Yeah, no. Doug, they aren't design rule compatible. Same goes for the M3, I'd bet you it's going to be on N3B.

If A17 is going to be on N3E as soon as that process is available, I still think it is quite likely Apple does not produce any N3B M3s and they are all N3E - to avoid the cost of having two versions of that design.

If there are no M3 Macs announced next month I think it is pretty safe to say we won't see them until next spring and if so we will know for sure they are N3E.

We will see about Intel. They may have decided to wait for N3E to avoid dealing with the issues of N3B. Apple was willing to do so because they needed the density for A17, but we've all seen the rumors that it will switch to N3E next year.

 

[Mopetar]

I don't know if Apple would bother doing a redesign of A17 on N3E. By the time they could, they'd just as well make A18 instead. It seems like everyone is avoiding N3B like the plague and TSMC probably can't wait to get rid of it.

It does mean that there's going to be more of a delay for AMD (or other companies) to get out products that aren't on N5 (or one of its derivatives) and potentially means that it may take until 2025 for some parts.

 

[Kepler_L2]

I don't know if Apple would bother doing a redesign of A17 on N3E. By the time they could, they'd just as well make A18 instead. It seems like everyone is avoiding N3B like the plague and TSMC probably can't wait to get rid of it.

It does mean that there's going to be more of a delay for AMD (or other companies) to get out products that aren't on N5 (or one of its derivatives) and potentially means that it may take until 2025 for some parts.

Turin-Dense is N3E and H1 2024.

 

[Mopetar]

Turin-Dense is N3E and H1 2024.

Is 3NE going to be ready in time for that? I e seen posts in other threads suggesting that the 3NE node would only be ready by mid-year. I don't know if that was based on anything other than speculation or rumors though.

 

[Abwx]

Or they were unable to optimize the arch-driven Cac increase enough to keep all-core clocks at Zen 4 level, even taking into account 4nm node PPA advantage, so a slight reduction in MT clocks seems reasonable and quite expected.
I'm afraid no more massive Cac optimizations aka Zen2->Zen3

If there s a frequency regression that will be on ST, on MT there s no way that it could be the case, smaller process gain efficency mainly with lower capacitance because
the other parameter that allow better perf/Watt, improved transconductance, is at odd with transistors shrinking.

 

[jpiniero]

Turin-Dense is N3E and H1 2024.

I still find that hard to believe AMD is that early on a node. Guess they could do the AMD patented 'announce a product but you can't actually buy it until 9 months later'

 

[jpiniero]

Is 3NE going to be ready in time for that? I e seen posts in other threads suggesting that the 3NE node would only be ready by mid-year. I don't know if that was based on anything other than speculation or rumors though.

TSMC said in July that N3E is starting volume production in Q4.

 

[Geddagod]

If there s a frequency regression that will be on ST, on MT there s no way that it could be the case, smaller process gain efficency mainly with lower capacitance because
the other parameter that allow better perf/Watt, improved transconductance, is at odd with transistors shrinking.

You're overhyping the shrink from N5 to N4 way too much, especially considering the 7950x boosts at like >5Ghz lol.
Fatter architecture causes increased power draw iso frequency. It gets more IPC sure, but that's not the point here. The potential ST frequency regression isn't likely due to a increase in power consumption, but because clocking wider cores super high is just hard, esp when you also have to balance it out with area.
The MT clock regression however, is likely due to potentially increased power consumption, as MT performance is much more limited by power draw.
We have seen this exact same pattern with Intel with Cypress Cove vs Skylake. They widened the core quite a bit, lost frequency iso power, though ST clocks here remained roughly the same. It's a valid expectation to imagine a zen 5 with something like 30% IPC, with a 5-10% increase in power consumption iso clock, and 200MHz shaved off in peak ST frequency.

 

[Kepler_L2]

Is 3NE going to be ready in time for that? I e seen posts in other threads suggesting that the 3NE node would only be ready by mid-year. I don't know if that was based on anything other than speculation or rumors though.

 

[H433x0n]

You're overhyping the shrink from N5 to N4 way too much, especially considering the 7950x boosts at like >5Ghz lol.
Fatter architecture causes increased power draw iso frequency. It gets more IPC sure, but that's not the point here. The potential ST frequency regression isn't likely due to a increase in power consumption, but because clocking wider cores super high is just hard, esp when you also have to balance it out with area.
The MT clock regression however, is likely due to potentially increased power consumption, as MT performance is much more limited by power draw.
We have seen this exact same pattern with Intel with Cypress Cove vs Skylake. They widened the core quite a bit, lost frequency iso power, though ST clocks here remained roughly the same. It's a valid expectation to imagine a zen 5 with something like 30% IPC, with a 5-10% increase in power consumption iso clock, and 200MHz shaved off in peak ST frequency.

I’d be shocked if ST frequency only dipped by 200mhz. I don’t know if a core has ever gotten 30-40% wider and only had to give up 3-4% frequency in exchange while on a similar node. Such a feat is possible but it’d require way more silicon real estate and a much larger power budget and that doesn’t seem to be AMD’s style.

I wonder if AMD even knows where final frequency for Zen 5 client ends up. I’m sure they’re got simulations / projections but I’m not sure how accurate those are at the edge of the VF curve that client usually runs at.