Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[DisEnchantment]

So, it remains to be seen. It would be surprising to me if AMD did not make any improvement to V-Cache capacity in Zen 4. Since we know that the stacked die is the same 64 MB as Zen 3, 2 layers would be the only way to add extra capacity.

Zen 3 V-Cache can have many stacks of SRAM, they did not do it probably because of excessive latency and power.

https://twitter.com/x/status/1399671731112091649

Also Andreas Schilling showed the BIOS config for the 8 Hi Stacks.

I doubt there is something about 3D stacking that is inherently very expensive. I think the concern that AMD may have is volume, if TSMC will have a sufficient capacity for millions of chips to be stacked.

Since 5800X3D is one of the most if not the most highest selling AM4 chip I would say the economics are slowly working out. There is no dearth of 5800X3D at all. Chip can be had for less than 350 bucks. Many current and upcoming products are chiplet based with advanced packaging. 5800X3D, 7XX0X3D, Milan-X, Genoa-X, RDNA3, MI300, STX (supposedly), RDNA4(supposedly)
This year TF-AMD's biggest packaging facility will come online in Malaysia. TSMC's AP2C came online in 2H2022.

 

[DisEnchantment]

The market is there for both to coexist, say a monolithic Strix Point for 10W-25W and DT derived chiplet based APU for 25W-65W. Just like with Zen 4 for instance; Dragon Range, Phoenix and Phoenix2.
AMD cannot ignore the low power but price sensitive sensitive segment, wherein the likes of Qualcomm SoCs will play and they will blow their trumpet hard.
Likely for Low Power Mobile it may not even be a clear cut advantage to go with chiplets if you consider the fact that TSMC is now offering FinFlex, unless AMD is planning 220mm2+ dies for the ultra low power and we know that is not happening.

With FinFlex they could use 2-2 Fins for the P cores and 2-1 Fins for E Core, cache and CUs since they can clock them lower. Should help with density and efficiency greatly.
If PHX2 is an indicator of future direction, likely the efficiency cores would be something like 8C Zen 5 with half the L3 using the 2-1 Fins and 4C performance cores on 2-2 Fins with full L3, for a total of 12C/24T Zen 5 cores. Or something like this arrangement. Putting Zen 4c in a Zen 5 SoC would land AMD in a similar situation of AVX512 support in ADL, since we know AMD hinted of new AI instructions coming for Zen 5.
N3E 2-1 fins don't have a regression vs N5 2-2 fins in performance. Good fit for CUs and E Cores. And the density gains are very significant vs N5 2-2 fins, 1.56x vs 1.38x for N3 2-2 Fins for logic, for which there are lots of within the CUs

The high end mobile though would be covered by the mainstream DT APUs, this is apparent that AMD needs to address this following the footsteps of Intel.

But lets see if the new interconnects can be energy frugal enough that AMD can address the 10W-150W market with a single unified chiplet approach. If this is the case, then Zen 5 would be formidable across the entire TDP range and provide AMD with an amazing product flexibility. This is why I feel the interconnects and packaging are the most interesting part of MI300 and can be a key lever for AMD to scale performance and efficiency across all segments.

 

[bakyt115]

Oh my God.
How we easily forget RTGs false claims about phoenix.

https://www.club386.com/wp-content/uploads/2022/06/AMD-Phoenix-Design-Leak.jpg

 

[Det0x]

Hope we get the APU 8000 series memory controller or better when Zen5 finally releases
Its doing pretty decent when comboed with a good memory OC motherboard

• Dual channel 9800MT/s
• 2550mhz FCLK (will be hard to match this with chiplet based architecture -> regular Zen4 caps out at 2200mhz FCLK)
• Delidded and paste is replaced with LM

I'm so close to breaking the magical 18k memscore in GB3 with this setup

 

[Thunder 57]

Just saying that the technical info is far more valuable than pricing info. And if @adroc_thurston is wrong on pricing info, it's really a minor thing compared to his contribution of technical information.

I just don't get why he has such credibility. Based on what history? Looks like his April launch date is wrong too. People call out MLID for making crap up, I can't help but feel the same way here.

 

[Fjodor2001]

Having worked fairly high in the computer retail industry, and been a hobbyist for longer, I know internal and external release dates can differ wildly, the former changing multiple times. As in, internal to the company the idea is to release on X date, but if they've not announced it publicly (external) it is subject to change until the last minute.

AMD themselves haven't announced anything at all, and this thread has already bounced around decent ideas why that is so; to wit: if Zen4 is selling at or beyond their predictions, why introduce a new architecture when Intel's latest is mediocre extra battery life in laptops, or furnace inducing 3% top performance on desktop; if Zen5 *is* that good, announcing at any time before the last second might take the impetus for Zen4 sales (see previous point) and why would a company risk that. It's highly possible that Zen5 was planned to release now, but it's since been decided they can hold off for the "back to school" season, ie, a massive 2 months...

People in this thread being butthurt that Zen5 isn't out in a 8 days isn't the dunk on adroc that you seem to think it is. I don't believe he's ever said he works for AMD, and is subject to ongoing and last minute changes in info. He has so far not pulled a MILD, and changed the release date in recent posts to suit his narrative, and deleted all his old posts. I am also not saying he's not lying, I'm just saying we still don't have proof either way, so calm your clams.

But why trust him over any other person on this forum? What history of correct leak information does he have? None that I know of so far.

 

[carrotmania]

Would you rather just have me say Zen5 DT will be 50+% IPC, 10 GHz, 64C/128T, at 65W TDP, and $499 for top SKU, and that I got the info from Lisa Su directly? Would that make you happy?

Reductio ad absurdum, a poor last resort...

I'm also very chill. I've made 2 (OK, 3 now) posts. Hardly a novel. You are the one jumping down another members throat over ALL his "information" being wrong, based on a single point of data, a date, which are known to shift until the very last second, being off. You have NOTHING else to back you up. I understand neither does he, and again, I am not advocating for him one way or another.

Your dismissing everything he's posted (which again, has been a single line of information, it hasn't changed with changing circumstances, unlike MILD etc) over a single specious point of data is disingenuous at best, and counterintelligence at worst.

 

[dr1337]

I think everyone is wrong and just like they've always been the past 4-5 years, AMD is tight lipped and none of the "leaks" are more than 75% accurate.

I even foresee a near future where all of these rumor mongers all begin to hinge on one or two specific benchmarks to suddenly validate their wild predictions.

I've been actually deep in tech since the days of sandy bridge, and these leaker names like MLID and AdoredTV didn't come out of the woodwork until the time of 2018/2019 when techtubers became a gold mine. I think its obvious a lot of people stand to gain by grasping at straws to build up clout and thus generate streams of revenue/help bolster their existing income streams.

I've been re-reading the RDNA2 speculation thread lately to try and see which leakers were and weren't correct and its very interesting how much the forum has changed as of late. People seemed to get way more hyped about little tidbits these days. Zen 5 is going to be good, if not then it will be AMDs worst blunder since bulldozer. But I think people should be more proactive to ignore hype and wild claims, in my opinion.

 

[BorisTheBlade82]

Okay, so now the layout of MI300 gets clearer:

https://twitter.com/x/status/1627720114823888922

 

[DisEnchantment]

The rumors say? 🙂 This is all out in the open with extreme detail for months..

https://twitter.com/x/status/1427612246411292672

View attachment 52061


View attachment 52062

I have been thinking about max TDP for a while, but I would like to calculate how much power per chiplet to have clearer picture. Both Genoa and Bergamo chiplets have max default TDP of 360W, let's assume Turin and Bergamo 5c with max cores as rumored (that would be 192 Zen 5 cores and 256 Zen 5c cores) have max TDP of 600W per socket. Below is my calculation:

	Raphael	Genoa	Bergamo	Turin	Bergamo 5c
CPU Architecture	Zen 4	Zen 4	Zen 4c	Zen 5	Zen 5c
TSMC - Power Efficiency	N5	N5	N5	N4P - 22%	N3E - 34%
Cores Per Chiplet	8	8	16	16	32
Max CCD	2	12	8	12	8
L3 Cache Per Chiplet	32MB	32MB	32MB	64MB	64MB
Max L3 Caches	64MB	384MB	256MB	768MB	512MB
TDP	65W	360W	360W	600W	600W
Power per chiplet	30W	30W	45W	50W	75W
Power per Core	3.75W	3.75W	2.81W	3.13W	2.34W

• Both Bergamo and Bergamo 5c could only have 8 chiplets per socket cause they are having bigger die size due to double core counts. OTOH, their L3 caches would be smaller than Genoa/Turin, you can't have both more core counts and bigger L3 cache at the same time.
• With power efficiency improvements, I believe Turin would fit in double core counts with same socket. I also expecting some clock regression and higher IPC from Zen 5 architecture. What do you think?

From Genoa thermal design guide, Max IOD power is 120W around. Which gives about 2.91W/Core Max.

From Execufix figure, Turin max TDP is 600W, assuming IOD remains unchanged at 120W that's 5W/Core.

Unless AMD goes full retard we can assume they will not use 1.7x more power staying at the same core count.

So excluding IOD power of 120W,
Turin 96C@480W=5W/Core or 1.71x that of Genoa.
Turin 128C@480W=3.75W/Core or 1.3x that of Genoa
Turin 144C@480W=3.33W/Core or 1.14x that of Genoa
Turin 160C@480W=3W/Core or 1x that of Genoa.

Turin should boost core count significantly. Either that or Turin is a fail of epic proportions considering N4P (assuming Turin is not using N3E) have a significant efficiency gain over N5.

 

[Markfw]

Lisa Su has done great stuff for AMD, but focusing on maintaining margins above all else will risk them everything. Just look at Intel. There was a time they worshiped margins.

This I have to agree with. While a sane corporate goal and good for investors, they need to start focusing on market share, and that means not making the most money TODAY.

While the server market is pretty well locked up at the moment and for at least a year or 2, they need to start thinking across the board. I don't think they have the OEMS in their pocket yet like Intel.

 

[Joe NYC]

Correct, and I think too much was made of that side comment of hers. Demand is falling industry-wide. Bloating the channel with product is a bad move in the middle of a global financial meltdown (which may get worse later this year/next year). It's important to remember that, at the time of that call, Raphael-X didn't even exist on the market, while Raphael prices were in steady decline.

Despite AMD "holding back product", their flagship CPU was still losing market value. Their top seller by volume was (and probably still is) AM4-based Vermeer/Vermeer-X. The only product they had at the time with an inflated ASP was the 7900XTX.

Yes, there were articles from Neanderthals of finance - like Videocardz - who posted really brain dead articles, trying to sound like they have a "scoop" they uncovered, that AMD "admitted" to be under-shipping. (this was to reduce bloated inventories in the channel)

But it was a good reminder not to rely on intelligence of people who write these articles.

PS: Videocardz blocked me on Twitter for mocking the article, and now, going back, I see they stealth deleted it and their posts on Twitter pointing to it.

 

[eek2121]

A reminder to the new folks and the uninformed here. RGT and MLID are not valid sources of information. Quite often, they state the exact opposite of what eventually ends up getting released.

 

[Saylick]

how blurry the shot was should have been a dead giveaway it doesn't have the noisy fine grain a slipped shot takes from a partner testing an es. what's with the yellow animal?

My reaction to someone not knowing what the "yellow animal" is:

 

[gdansk]

It literally is.
That's like the future of all CPU cores, not just AMD.
Dark si is cheapo, everything else is not.
N3/N2/onwards nodes are rich in logic scaling and nothing ever else.
Can't spam SRAM, can't scale the frequency anymore so the only choice remains.

like what?

that's not how you design anything lol

It goes way back. People hyped K10 to the moon. Or more recently the claims Zen 2 would be 5GHz. Or bondrewd's misinterpretation of RDNA3.

Sometimes reality does not end up matching unsourced performance projections.

What are you talking about? adroc just killed my expectation that AMD finally would increase the link speed (per cycle, I know I know) with Zen 5. I'm seriously bummed here, lol.

They'll cut it in half if you don't stop talking about it.

 

[jpiniero]

RDNA3 perform well in tests but badly according to the usual urban legends rehashed ad nauseam, what they lack is cards that cover the mid range segments, at this point they only have the 7900XT/XTX at the upper range and the 7600 at the bottom, money is made between thoses two segment for a big part.

Grafikkarten-Rangliste 2024: GPUs im Vergleich

Welche Grafikkarte kaufen? Für den März gibt es Empfehlungen mit Nvidia GeForce RTX 4000, AMD Radeon RX 7000 und Intel Arc.

www.computerbase.de

So what did badly panout according to these numbers..?

AMD clearly missed their performance expectations. And it's also quite obvious that they delayed N32 until RDNA2's supply runs low because N32 is only about the same performance as a deep cut N21 (6800 XT) and only mildly cheaper. It's taken AMD and the AIBs ages to draw down the supply.

Edit: Will say that I am wondering how much interest from OEMs AMD expects from Strix Halo.

 

[blackangus]

Do you suppose you could take this apple thing to the apple thread ?

I brought apple up on context of nodes available in the zen 5 time frame and capacity at TSMC, which should be fair game.
After that Adroc brought them up again, which is why my reply was in context with.

 

[SpudLobby]

https://twitter.com/x/status/1693975687919800555

https://twitter.com/x/status/1694293526157344975

Well, if this is true, and it looks legit for now - even less competition for AMD in the performance market with Zen 5. 1600 @ 3.4GHz is higher than the X3 but barely. TBD on power. There's also further delay apparently.

Then we've got this. Almost certainly due to anticipated lower demand IMHO, at least at the prices they can afford to charge - BOM is indeed going to rise now that Intel's ramping i4/i3, using TSMC's leading nodes, etc.

https://twitter.com/dylan522p/status/1693981897309761657

It's AMD's to lose to some extent with Zen 5 in mobile client parts.

 

[Markfw]

I was just giving out a bit of concext about 2024 CPU landscape.
What was supposed to be a hyper-competitive year is now a wasteland with one champion standing triumphant.

Somehow one reply turned into 3 pages of NO Zen 5, thats why I replied.

 

[Glo.]

32GB of LPDDR5x is low in my opinion even If Vram is dynamically allocated to IGP, because It is not upgradeable.

32 GB of RAM for APUs/SOCs are minimum right now

64 is the optimum .

 

[inf64]

The internal AMD slide is the one that says that not MLID

Others have addressed that, read up in the thread. It's not my fault that MLID has no IQ capacity to interpret the data he has been fed to.

 

[msj10]

I'm not blaming him for the number lol, I'm just saying he has troubles interpreting data he has been spoon fed. That is why he put such a wide range of 15-25% on his "prediction", as he has no idea what the changes listed on one of the slides even mean.

you can't just look at a microarchitecture block diagram and come up with an accurate IPC figure. just look at A17 with all the changes and it ended up with just a 3% IPC uplift

 

[Timorous]

Why would someone need an NDA for an internal document.

Where I work the business updates are under NDA and I don't get access to the presentation, the slide deck is shared via video / screen share rather than giving people the document itself.

 

[Markfw]

I mean I just posted this, but no one is using Bergamo for just raw MT perf. Oh sure, technically, Bergamo even beats Genoa in raw MT perf, but again, even AMD is calling these cloud processors, not HPC processors. The reason why is pretty obvious.

<snip>

In which case we get Turin being 48% more performant than GNR, which doesn't shrink the gap between how much SPR loses to Genoa... but it drastically improves the efficiency gap since both of these CPUs will be at 500 watts. Me personally? I think the gap is going to be closer to ~30%, but we will see.
(final disclaimer, ik this is a massively oversimplified projection based on leaks, not including stuff like memory bandwidth or SMT vs 1T, etc etc, but this was just for fun anyway

I think this is basically what I am saying. AMD rules servers in every respect today, and for the foreseeable future. I saw the post about the IT manager thinking "I will never get fired for buying Intel", but I am so sick of that. I can not believe for over 5 years, and with power getting more and more expensive that they won't rethink. They could get a raise if they told their manager "look, this is 30% more efficient on power and is faster". Not to mention in data center, the amount is arguable, but 1 watt saved = 2-3 watts saved due to AC and to APS support.

 

[coercitiv]

Likelihood of increasing IPC while decreasing power is low.

Zen 3 vs. Zen 2

• 19% IPC increase
• same node class, but improved
• slightly higher clocks
• bigger die
• ISO power
• right in our face

Spoiler

The biggest problem in this thread isn't this discussion point though, but rather whether folks around here are going to accept the rude verdicts of a poster as gospel or demand the minimum of proof and decorum.