- Dec 26, 2004
- 11,905
- 148
- 101
For this project, we are given that there is a Logic F with inputs (A, B, C, D) and the minterms (high outputs or "1's") for these given inputs are (0,4,5,6,7,8,12.) He wants a minimized SOP form for these inputs. The first thing I did was draw a K-map for this problem: Here
looked this K-map over plenty of times and see nothing wrong with it. I came up with the minimized SOP expression of (not C and not D) + (not A and B). I next drew a schematic for this specific logic: Here
From that, I wrote my VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity LogicF is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end LogicF;
architecture dataflow of LogicF is
signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
signal wire5: std_logic;
signal wire6: std_logic;
begin
-- Y <= (not C and not D) or (not A and B); This line is commented out
wire1 <= not A;
wire2 <= B;
wire3 <= not C;
wire4 <= not D;
wire5 <= wire1 and wire2;
wire6 <= wire3 and wire4;
Y <= wire5 or wire6;
end dataflow;
From that VHDL I made Altera interpret it as a schematic and it gave me EXACTLY what I have drawn in my schematic previously. I compiled the code and it worked fine. I set the clock for input A to 10ms, B 20ms, C 40ms, and D 80ms to give me the binary counting order for all inputs and ended my simulation at 100ms. The problem occurs when my output is determined. It does not match my truth table (minterms given) at all. My output (Y) can be seen Here. It is the lower most waveform. It is reading a high from 0000 -> 1100 and for 0110. These are not my highs at all. The truth table that I made for what are supposed to be my outputs is here.
I am really at a loss. I went through this so many times and I still cannot figure out what I'm doing wrong. The prof couldn't make his office hours today again so I got no help today either. Hopefully someone here has some idea of what I'm trying to do. Any help would be appreciated.... Thanks.
looked this K-map over plenty of times and see nothing wrong with it. I came up with the minimized SOP expression of (not C and not D) + (not A and B). I next drew a schematic for this specific logic: Here
From that, I wrote my VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity LogicF is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end LogicF;
architecture dataflow of LogicF is
signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
signal wire5: std_logic;
signal wire6: std_logic;
begin
-- Y <= (not C and not D) or (not A and B); This line is commented out
wire1 <= not A;
wire2 <= B;
wire3 <= not C;
wire4 <= not D;
wire5 <= wire1 and wire2;
wire6 <= wire3 and wire4;
Y <= wire5 or wire6;
end dataflow;
From that VHDL I made Altera interpret it as a schematic and it gave me EXACTLY what I have drawn in my schematic previously. I compiled the code and it worked fine. I set the clock for input A to 10ms, B 20ms, C 40ms, and D 80ms to give me the binary counting order for all inputs and ended my simulation at 100ms. The problem occurs when my output is determined. It does not match my truth table (minterms given) at all. My output (Y) can be seen Here. It is the lower most waveform. It is reading a high from 0000 -> 1100 and for 0110. These are not my highs at all. The truth table that I made for what are supposed to be my outputs is here.
I am really at a loss. I went through this so many times and I still cannot figure out what I'm doing wrong. The prof couldn't make his office hours today again so I got no help today either. Hopefully someone here has some idea of what I'm trying to do. Any help would be appreciated.... Thanks.
Facebook
Twitter