xbit on banias

[ElFenix]

ripped from AT news

the p3 lives! a meg of L2 and 1.7 GHz... i'm guessing ddr or qdr FSB, prefetch, maybe even the ability to access L2 every cycle rather than every other (though i'm not sure of the feasibility of that). of course, thats pure speculation on my part, thought the tualatin p3s have prefetch so thats not a stretch. should kill the p4-m... how is intel going to sell a lower MHz part as higher performance than the p4-m? heheh what if they have model numbers too? 😛

 

[SexyK]

I thought Banias was going to be there new "super low power" CPU, and no compete with the P4M in terms of performance. Maybe I'm wrong though. Interesting article either way.

Kramer

 

[dexvx]

They said a 1.5Ghz Banias should beat a 2.5-2.6Ghz P4-M (it will be approximately that speed once its released).

 

[ElFenix]

well from the size of it and the fact that drawing up a whole new architecture would take a while longer than intel has put into it, it looks like a p3 with some things straightened out to get it to ramp higher. the fact that the first steppings of tualatin easily reached 1.5GHz means they didn't have to try too hard. a p3 at 1.7 with prefetch/ddr or qdr fsb/1 meg l2 would kill a p4 at the same speed. probably about even with a 2.4 or 2.5, judging by where the p4 debuted at in relation to the p3.

 

[Rand]

Quite interesting, I'm expecting it to be a dirivative of the P6 core, paired with elements of the FSB.
I do rather like the emphasis on L2 cache, the more L2 cache the less often the system will be forced to access main memory or the HDD which will help to save battery life. And certainly cache consumes significantly less power then processing logic.

I'm not sure about jumping to 2MB L2 on the .09u process though, after 1MB I suspect you'll see severely diminishing benefits, I'd rather 1.5MB L2 and perhaps some other modifications.

Undoubtedly Intel's done simulatrions to determine what is potentially the most efficient use of resources however.