X25-M(V) erase block size?

[trx]

On the Internet I've found two different oppinions about erase block size of Intel's X25-M (and X25-V) SSDs: 128kB and 512kB

128kB:
http://techreport.com/articles.x/15433
Intel gives an example in which a host system generates a 4KB write request that, thanks to a drive's 128KB erase block size, actually incurs a 128KB NAND write. Dividing the NAND write size by the request size yields the amplification factor, which is 32 in this case. Intel says the X25-M's write-amplification factor is extremely low at 1.1, while "traditional" SSDs have much higher amplification factor of 20.

512kB:
http://www.anandtech.com/show/2614/3
Group a bunch of cells together and you've got a page. A page is the smallest structure you can program (write to) in a NAND flash device. In the case of most MLC NAND flash each page is 4KB. A block consists of a number of pages, in the Intel MLC SSD a block is 128 pages (128 pages x 4KB per page = 512KB per block = 0.5MB). A block is the smallest structure you can erase. So when you write to a SSD you can write 4KB at a time, but when you erase from a SSD you have to erase 512KB at a time.

http://www.xbitlabs.com/articles/storage/display/intel-x25m-ssd_2.html
For the X25-M this block is as large as 128 pages or 512 kilobytes or half a megabyte. As a result, if there is a request to erase (or rewrite) one page, the drive has to erase 128 pages.

and then again, even on Intel's community forum I've found both 128kB and 512kB info:

128kB:
http://communities.intel.com/message/28730#28730

512kB:
http://communities.intel.com/message/68942#68942


So, is the size of erase block on X25-M(V) 128kB or 512kB ?

Thx.

 

[IntelUser2000]

Few months ago, I was searching for part numbers on the flash memory used on the Intel SSD drives. The page sizes on the MLC chips can vary, but only from 512KB to 1024KB. 128KB block sizes are only on the X25-E SLC drives.

The confusion between 128KB and 512KB page sizes probably stemmed because each page is 4KB and there are 128 pages in a block, for 512KB block sizes.

 

[trx]

Thx.

I guess there's no way to make smaller page size then the one on MLC chip itself.

I just cant understand why should one (Intel) hide some information like this.
I've tried to contact Intel's support explaining I need that info to correctly align writes thus lowering wearing and prolonging SSD's life.
All I've got is some story about that it's complicated and it depends how operating system manipulates filesystem, and so on...

 

[Makaijin]

Since 512kb is a multiple of 128kb, why not just align the partition assuming it's 512kb? It'll still be aligned either way.

 

[trx]

aligning partition on 512kB is good thing to do (I've done that already), but I have a chance to align filesystem writes, too. aligning filesystem writes to block size higher then needed leaves filesystem with much less options during writes.

btw, about aligning filesystem writes - I'm using linux.